------------- Registers -- -------------
subtype CH0_CC_A_Field is HAL.UInt16;
subtype CH0_CC_B_Field is HAL.UInt16;
type CH0_CC_Register is record
A : CH0_CC_A_Field := 16#0#;
B : CH0_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH0_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH0_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH0_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH0_CTR_CH0_CTR_Field is HAL.UInt16;
type CH0_CTR_Register is record
CH0_CTR : CH0_CTR_CH0_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH0_DIV_FRAC_Field is HAL.UInt4;
subtype CH0_DIV_INT_Field is HAL.UInt8;
type CH0_DIV_Register is record
FRAC : CH0_DIV_FRAC_Field := 16#0#;
INT : CH0_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH0_TOP_CH0_TOP_Field is HAL.UInt16;
type CH0_TOP_Register is record
CH0_TOP : CH0_TOP_CH0_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH1_CC_A_Field is HAL.UInt16;
subtype CH1_CC_B_Field is HAL.UInt16;
type CH1_CC_Register is record
A : CH1_CC_A_Field := 16#0#;
B : CH1_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH1_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH1_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH1_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH1_CTR_CH1_CTR_Field is HAL.UInt16;
type CH1_CTR_Register is record
CH1_CTR : CH1_CTR_CH1_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH1_DIV_FRAC_Field is HAL.UInt4;
subtype CH1_DIV_INT_Field is HAL.UInt8;
type CH1_DIV_Register is record
FRAC : CH1_DIV_FRAC_Field := 16#0#;
INT : CH1_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH1_TOP_CH1_TOP_Field is HAL.UInt16;
type CH1_TOP_Register is record
CH1_TOP : CH1_TOP_CH1_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH2_CC_A_Field is HAL.UInt16;
subtype CH2_CC_B_Field is HAL.UInt16;
type CH2_CC_Register is record
A : CH2_CC_A_Field := 16#0#;
B : CH2_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH2_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH2_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH2_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH2_CTR_CH2_CTR_Field is HAL.UInt16;
type CH2_CTR_Register is record
CH2_CTR : CH2_CTR_CH2_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH2_DIV_FRAC_Field is HAL.UInt4;
subtype CH2_DIV_INT_Field is HAL.UInt8;
type CH2_DIV_Register is record
FRAC : CH2_DIV_FRAC_Field := 16#0#;
INT : CH2_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH2_TOP_CH2_TOP_Field is HAL.UInt16;
type CH2_TOP_Register is record
CH2_TOP : CH2_TOP_CH2_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH3_CC_A_Field is HAL.UInt16;
subtype CH3_CC_B_Field is HAL.UInt16;
type CH3_CC_Register is record
A : CH3_CC_A_Field := 16#0#;
B : CH3_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH3_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH3_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH3_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH3_CTR_CH3_CTR_Field is HAL.UInt16;
type CH3_CTR_Register is record
CH3_CTR : CH3_CTR_CH3_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH3_DIV_FRAC_Field is HAL.UInt4;
subtype CH3_DIV_INT_Field is HAL.UInt8;
type CH3_DIV_Register is record
FRAC : CH3_DIV_FRAC_Field := 16#0#;
INT : CH3_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH3_TOP_CH3_TOP_Field is HAL.UInt16;
type CH3_TOP_Register is record
CH3_TOP : CH3_TOP_CH3_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH4_CC_A_Field is HAL.UInt16;
subtype CH4_CC_B_Field is HAL.UInt16;
type CH4_CC_Register is record
A : CH4_CC_A_Field := 16#0#;
B : CH4_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH4_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH4_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH4_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH4_CTR_CH4_CTR_Field is HAL.UInt16;
type CH4_CTR_Register is record
CH4_CTR : CH4_CTR_CH4_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH4_DIV_FRAC_Field is HAL.UInt4;
subtype CH4_DIV_INT_Field is HAL.UInt8;
type CH4_DIV_Register is record
FRAC : CH4_DIV_FRAC_Field := 16#0#;
INT : CH4_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH4_TOP_CH4_TOP_Field is HAL.UInt16;
type CH4_TOP_Register is record
CH4_TOP : CH4_TOP_CH4_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH5_CC_A_Field is HAL.UInt16;
subtype CH5_CC_B_Field is HAL.UInt16;
type CH5_CC_Register is record
A : CH5_CC_A_Field := 16#0#;
B : CH5_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH5_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH5_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH5_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH5_CTR_CH5_CTR_Field is HAL.UInt16;
type CH5_CTR_Register is record
CH5_CTR : CH5_CTR_CH5_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH5_DIV_FRAC_Field is HAL.UInt4;
subtype CH5_DIV_INT_Field is HAL.UInt8;
type CH5_DIV_Register is record
FRAC : CH5_DIV_FRAC_Field := 16#0#;
INT : CH5_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH5_TOP_CH5_TOP_Field is HAL.UInt16;
type CH5_TOP_Register is record
CH5_TOP : CH5_TOP_CH5_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH6_CC_A_Field is HAL.UInt16;
subtype CH6_CC_B_Field is HAL.UInt16;
type CH6_CC_Register is record
A : CH6_CC_A_Field := 16#0#;
B : CH6_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH6_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH6_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH6_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH6_CTR_CH6_CTR_Field is HAL.UInt16;
type CH6_CTR_Register is record
CH6_CTR : CH6_CTR_CH6_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH6_DIV_FRAC_Field is HAL.UInt4;
subtype CH6_DIV_INT_Field is HAL.UInt8;
type CH6_DIV_Register is record
FRAC : CH6_DIV_FRAC_Field := 16#0#;
INT : CH6_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH6_TOP_CH6_TOP_Field is HAL.UInt16;
type CH6_TOP_Register is record
CH6_TOP : CH6_TOP_CH6_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH7_CC_A_Field is HAL.UInt16;
subtype CH7_CC_B_Field is HAL.UInt16;
type CH7_CC_Register is record
A : CH7_CC_A_Field := 16#0#;
B : CH7_CC_B_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type CH7_CSR_DIVMODE_Field is
div,
level,
rise,
fall)
with Size => 2;
Fractional divider operation is gated by the PWM B pin.
Counter advances with each rising edge of the PWM B pin.
Counter advances with each falling edge of the PWM B pin.
type CH7_CSR_Register is record
EN : Boolean := False;
PH_CORRECT : Boolean := False;
A_INV : Boolean := False;
B_INV : Boolean := False;
DIVMODE : CH7_CSR_DIVMODE_Field := RP2040_SVD.PWM.div;
PH_RET : Boolean := False;
PH_ADV : Boolean := False;
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH7_CTR_CH7_CTR_Field is HAL.UInt16;
type CH7_CTR_Register is record
CH7_CTR : CH7_CTR_CH7_CTR_Field := 16#0#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH7_DIV_FRAC_Field is HAL.UInt4;
subtype CH7_DIV_INT_Field is HAL.UInt8;
type CH7_DIV_Register is record
FRAC : CH7_DIV_FRAC_Field := 16#0#;
INT : CH7_DIV_INT_Field := 16#1#;
Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype CH7_TOP_CH7_TOP_Field is HAL.UInt16;
type CH7_TOP_Register is record
CH7_TOP : CH7_TOP_CH7_TOP_Field := 16#FFFF#;
Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type EN_CH_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
Val : HAL.UInt8;
when True =>
Arr : EN_CH_Field_Array;
end case;
end record
with Unchecked_Union, Size => 8;
type EN_CH_Field_Array is array (0 .. 7) of Boolean
with Component_Size => 1, Size => 8;
type EN_Register is record
CH : EN_CH_Field := (As_Array => False, Val => 16#0#);
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type INTE_CH_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
Val : HAL.UInt8;
when True =>
Arr : INTE_CH_Field_Array;
end case;
end record
with Unchecked_Union, Size => 8;
type INTE_CH_Field_Array is array (0 .. 7) of Boolean
with Component_Size => 1, Size => 8;
type INTE_Register is record
CH : INTE_CH_Field := (As_Array => False, Val => 16#0#);
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type INTF_CH_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
Val : HAL.UInt8;
when True =>
Arr : INTF_CH_Field_Array;
end case;
end record
with Unchecked_Union, Size => 8;
type INTF_CH_Field_Array is array (0 .. 7) of Boolean
with Component_Size => 1, Size => 8;
type INTF_Register is record
CH : INTF_CH_Field := (As_Array => False, Val => 16#0#);
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type INTR_CH_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
Val : HAL.UInt8;
when True =>
Arr : INTR_CH_Field_Array;
end case;
end record
with Unchecked_Union, Size => 8;
type INTR_CH_Field_Array is array (0 .. 7) of Boolean
with Component_Size => 1, Size => 8;
type INTR_Register is record
CH : INTR_CH_Field := (As_Array => False, Val => 16#0#);
Reserved_8_31 : HAL.UInt24 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type INTS_CH_Field
(As_Array : Boolean := False)
is record
case As_Array is
when False =>
Val : HAL.UInt8;
when True =>
Arr : INTS_CH_Field_Array;
end case;
end record
with Unchecked_Union, Size => 8;
type INTS_CH_Field_Array is array (0 .. 7) of Boolean
with Component_Size => 1, Size => 8;
type INTS_Register is record
CH : INTS_CH_Field;
Reserved_8_31 : HAL.UInt24;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
PWM_Periph : aliased PWM_Peripheral
with Import, Address => PWM_Base;
type PWM_Peripheral is record
CH0_CSR : aliased CH0_CSR_Register;
CH0_DIV : aliased CH0_DIV_Register;
CH0_CTR : aliased CH0_CTR_Register;
CH0_CC : aliased CH0_CC_Register;
CH0_TOP : aliased CH0_TOP_Register;
CH1_CSR : aliased CH1_CSR_Register;
CH1_DIV : aliased CH1_DIV_Register;
CH1_CTR : aliased CH1_CTR_Register;
CH1_CC : aliased CH1_CC_Register;
CH1_TOP : aliased CH1_TOP_Register;
CH2_CSR : aliased CH2_CSR_Register;
CH2_DIV : aliased CH2_DIV_Register;
CH2_CTR : aliased CH2_CTR_Register;
CH2_CC : aliased CH2_CC_Register;
CH2_TOP : aliased CH2_TOP_Register;
CH3_CSR : aliased CH3_CSR_Register;
CH3_DIV : aliased CH3_DIV_Register;
CH3_CTR : aliased CH3_CTR_Register;
CH3_CC : aliased CH3_CC_Register;
CH3_TOP : aliased CH3_TOP_Register;
CH4_CSR : aliased CH4_CSR_Register;
CH4_DIV : aliased CH4_DIV_Register;
CH4_CTR : aliased CH4_CTR_Register;
CH4_CC : aliased CH4_CC_Register;
CH4_TOP : aliased CH4_TOP_Register;
CH5_CSR : aliased CH5_CSR_Register;
CH5_DIV : aliased CH5_DIV_Register;
CH5_CTR : aliased CH5_CTR_Register;
CH5_CC : aliased CH5_CC_Register;
CH5_TOP : aliased CH5_TOP_Register;
CH6_CSR : aliased CH6_CSR_Register;
CH6_DIV : aliased CH6_DIV_Register;
CH6_CTR : aliased CH6_CTR_Register;
CH6_CC : aliased CH6_CC_Register;
CH6_TOP : aliased CH6_TOP_Register;
CH7_CSR : aliased CH7_CSR_Register;
CH7_DIV : aliased CH7_DIV_Register;
CH7_CTR : aliased CH7_CTR_Register;
CH7_CC : aliased CH7_CC_Register;
CH7_TOP : aliased CH7_TOP_Register;
EN : aliased EN_Register;
INTR : aliased INTR_Register;
INTE : aliased INTE_Register;
INTF : aliased INTF_Register;
INTS : aliased INTS_Register;
end record
with Volatile;