RP.Clock

Entities

Simple Types

Record Types

Subtypes

Constants

Subprograms

Description

Clock_Id

type Clock_Id is
   (GPOUT0, GPOUT1, GPOUT2, GPOUT3, REF, SYS, PERI, USB, ADC, RTC,
    PLL_SYS, GPIN0, GPIN1, PLL_USB, ROSC, XOSC);
Enumeration Literal
GPOUT0
GPOUT1
GPOUT2
GPOUT3
REF
SYS
PERI
USB
ADC
RTC
PLL_SYS
GPIN0
GPIN1
PLL_USB
ROSC
XOSC

Configure_PLL

procedure Configure_PLL
   (PLL    : PLL_Clock_Id;
    Config : PLL_Config)

Remember to switch clk_sys to another source before modifying PLL_SYS

Parameters
PLL
Config

Countable_Clock_Id

subtype Countable_Clock_Id is Clock_Id range REF .. RTC;

By default, the fractional part of the frequency counter result register is ignored. Setting Rounded = False includes the fractional frequency, which may include as much as 2048 KHz of error, depending on the value of Accuracy. Higher Accuracy values take longer to measure the clock, but produce more accurate results.

Disable

procedure Disable
   (CID : Clock_Id)
Parameters
CID

Enable

procedure Enable
   (CID : Clock_Id)
Parameters
CID

Enabled

function Enabled
   (CID : Clock_Id)
   return Boolean
Parameters
CID
Return Value

Frequency

function Frequency
   (CID      : Countable_Clock_Id;
    Rounded  : Boolean := True;
    Accuracy : UInt4 := 15)
    return Hertz

By default, the fractional part of the frequency counter result register is ignored. Setting Rounded = False includes the fractional frequency, which may include as much as 2048 KHz of error, depending on the value of Accuracy. Higher Accuracy values take longer to measure the clock, but produce more accurate results.

Parameters
CID
Rounded
Accuracy
Return Value

GP_Divider_Fraction

GP_Divider_Fraction : constant := 1.0 / (2 ** 8);

If GP_Divider is 0.0, then it represents (2.0 ** 16)

GP_Output

subtype GP_Output is Clock_Id range GPOUT0 .. GPOUT3;

GP_Source

subtype GP_Source is Clock_Id range REF .. XOSC;

Initialize

procedure Initialize
   (XOSC_Frequency     : XOSC_Hertz := 0;
    XOSC_Startup_Delay : XOSC_Cycles := 770_048)

See 2.16.3 Startup Delay for XOSC_Startup_Delay calculation. The default value is approximately 1ms with a 12 MHz crystal.

Parameters
XOSC_Frequency
XOSC_Startup_Delay

~64ms with a 12 MHz crystal

PLL_125_MHz

PLL_125_MHz : constant PLL_Config :=
   (FREF     => 12_000_000,
    REFDIV   => 1,
    FBDIV    => 125,
    POSTDIV1 => 6,
    POSTDIV2 => 2);

PLL_133_MHz

PLL_133_MHz : constant PLL_Config :=
   (FREF     => 12_000_000,
    REFDIV   => 1,
    FBDIV    => 133,
    POSTDIV1 => 6,
    POSTDIV2 => 2);

PLL_250_MHz

PLL_250_MHz : constant PLL_Config :=
   (FREF     => 12_000_000,
    REFDIV   => 1,
    FBDIV    => 125,
    POSTDIV1 => 6,
    POSTDIV2 => 1);

PLL_48_MHz

PLL_48_MHz : constant PLL_Config :=
   (FREF     => 12_000_000,
    REFDIV   => 1,
    FBDIV    => 64,
    POSTDIV1 => 4,
    POSTDIV2 => 4);

PLL_Clock_Id

subtype PLL_Clock_Id is Clock_Id
   with Static_Predicate => PLL_Clock_Id in PLL_SYS | PLL_USB;

2.18.2. Calculating PLL parameters PLL = (FREF / REFDIV) * FBDIV / (POSTDIV1 / POSTDIV2) Common configurations are included below. Use pico-sdk/src/rp2_common/hardware_clocks/scripts/vcocalc.py

PLL_Config

type PLL_Config is record
   FREF     : PLL_FREF_Field;
   REFDIV   : PLL_REFDIV_Field;
   FBDIV    : PLL_FBDIV_Field;
   POSTDIV1 : PLL_POSTDIV_Field;
   POSTDIV2 : PLL_POSTDIV_Field;
end record;

2.18.2. Calculating PLL parameters PLL = (FREF / REFDIV) * FBDIV / (POSTDIV1 / POSTDIV2) Common configurations are included below. Use pico-sdk/src/rp2_common/hardware_clocks/scripts/vcocalc.py

Record fields
FREF
REFDIV
FBDIV
POSTDIV1
POSTDIV2

PLL_FBDIV_Field

subtype PLL_FBDIV_Field is UInt12 range 16 .. 320;

2.18.2. Calculating PLL parameters PLL = (FREF / REFDIV) * FBDIV / (POSTDIV1 / POSTDIV2) Common configurations are included below. Use pico-sdk/src/rp2_common/hardware_clocks/scripts/vcocalc.py

PLL_FREF_Field

subtype PLL_FREF_Field is Hertz range 5_000_000 .. 800_000_000;

2.18.2. Calculating PLL parameters PLL = (FREF / REFDIV) * FBDIV / (POSTDIV1 / POSTDIV2) Common configurations are included below. Use pico-sdk/src/rp2_common/hardware_clocks/scripts/vcocalc.py

PLL_POSTDIV_Field

subtype PLL_POSTDIV_Field is UInt3 range 1 .. 7;

2.18.2. Calculating PLL parameters PLL = (FREF / REFDIV) * FBDIV / (POSTDIV1 / POSTDIV2) Common configurations are included below. Use pico-sdk/src/rp2_common/hardware_clocks/scripts/vcocalc.py

PLL_REFDIV_Field

subtype PLL_REFDIV_Field is UInt6 range 1 .. 63;

2.18.2. Calculating PLL parameters PLL = (FREF / REFDIV) * FBDIV / (POSTDIV1 / POSTDIV2) Common configurations are included below. Use pico-sdk/src/rp2_common/hardware_clocks/scripts/vcocalc.py

ROSC_Frequency

function ROSC_Frequency return Hertz
Return Value

Set_Divider

procedure Set_Divider
   (GP  : GP_Output;
    Div : GP_Divider)
Parameters
GP
Div

Set_Source

procedure Set_Source
   (GP     : GP_Output;
    Source : GP_Source)

GP will glitch if enabled while changing sources

Parameters
GP
Source

Set_SYS_Source

procedure Set_SYS_Source
   (Source : SYS_Clock_Id)
Parameters
Source

SYS_Clock_Id

subtype SYS_Clock_Id is Clock_Id range PLL_SYS .. XOSC;

XOSC_Cycles

subtype XOSC_Cycles is Natural;

XOSC_Hertz

subtype XOSC_Hertz is Hertz range 0 .. 15_000_000
   with Static_Predicate => XOSC_Hertz in 0 | 1_000_000 .. 15_000_000;

The special value 0 indicates that the XOSC is not available.