RP2040_SVD.DMA

Entities

Simple Types

• CH0_CTRL_TRIG_DATA_SIZE_Field
• CH0_CTRL_TRIG_RING_SIZE_Field
• CH0_CTRL_TRIG_TREQ_SEL_Field
• CH10_CTRL_TRIG_DATA_SIZE_Field
• CH10_CTRL_TRIG_RING_SIZE_Field
• CH10_CTRL_TRIG_TREQ_SEL_Field
• CH11_CTRL_TRIG_DATA_SIZE_Field
• CH11_CTRL_TRIG_RING_SIZE_Field
• CH11_CTRL_TRIG_TREQ_SEL_Field
• CH1_CTRL_TRIG_DATA_SIZE_Field
• CH1_CTRL_TRIG_RING_SIZE_Field
• CH1_CTRL_TRIG_TREQ_SEL_Field
• CH2_CTRL_TRIG_DATA_SIZE_Field
• CH2_CTRL_TRIG_RING_SIZE_Field
• CH2_CTRL_TRIG_TREQ_SEL_Field
• CH3_CTRL_TRIG_DATA_SIZE_Field
• CH3_CTRL_TRIG_RING_SIZE_Field
• CH3_CTRL_TRIG_TREQ_SEL_Field
• CH4_CTRL_TRIG_DATA_SIZE_Field
• CH4_CTRL_TRIG_RING_SIZE_Field
• CH4_CTRL_TRIG_TREQ_SEL_Field
• CH5_CTRL_TRIG_DATA_SIZE_Field
• CH5_CTRL_TRIG_RING_SIZE_Field
• CH5_CTRL_TRIG_TREQ_SEL_Field
• CH6_CTRL_TRIG_DATA_SIZE_Field
• CH6_CTRL_TRIG_RING_SIZE_Field
• CH6_CTRL_TRIG_TREQ_SEL_Field
• CH7_CTRL_TRIG_DATA_SIZE_Field
• CH7_CTRL_TRIG_RING_SIZE_Field
• CH7_CTRL_TRIG_TREQ_SEL_Field
• CH8_CTRL_TRIG_DATA_SIZE_Field
• CH8_CTRL_TRIG_RING_SIZE_Field
• CH8_CTRL_TRIG_TREQ_SEL_Field
• CH9_CTRL_TRIG_DATA_SIZE_Field
• CH9_CTRL_TRIG_RING_SIZE_Field
• CH9_CTRL_TRIG_TREQ_SEL_Field
• SNIFF_CTRL_CALC_Field

Record Types

• CH0_CTRL_TRIG_Register
• CH0_DBG_CTDREQ_Register
• CH10_CTRL_TRIG_Register
• CH10_DBG_CTDREQ_Register
• CH11_CTRL_TRIG_Register
• CH11_DBG_CTDREQ_Register
• CH1_CTRL_TRIG_Register
• CH1_DBG_CTDREQ_Register
• CH2_CTRL_TRIG_Register
• CH2_DBG_CTDREQ_Register
• CH3_CTRL_TRIG_Register
• CH3_DBG_CTDREQ_Register
• CH4_CTRL_TRIG_Register
• CH4_DBG_CTDREQ_Register
• CH5_CTRL_TRIG_Register
• CH5_DBG_CTDREQ_Register
• CH6_CTRL_TRIG_Register
• CH6_DBG_CTDREQ_Register
• CH7_CTRL_TRIG_Register
• CH7_DBG_CTDREQ_Register
• CH8_CTRL_TRIG_Register
• CH8_DBG_CTDREQ_Register
• CH9_CTRL_TRIG_Register
• CH9_DBG_CTDREQ_Register
• CHAN_ABORT_Register
• DMA_Peripheral
• FIFO_LEVELS_Register
• INTE0_Register
• INTE1_Register
• INTF0_Register
• INTF1_Register
• INTR_Register
• INTS0_Register
• INTS1_Register
• MULTI_CHAN_TRIGGER_Register
• N_CHANNELS_Register
• SNIFF_CTRL_Register
• TIMER_Register

Subtypes

• CH0_CTRL_TRIG_CHAIN_TO_Field
• CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Field
• CH10_CTRL_TRIG_CHAIN_TO_Field
• CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Field
• CH11_CTRL_TRIG_CHAIN_TO_Field
• CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Field
• CH1_CTRL_TRIG_CHAIN_TO_Field
• CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Field
• CH2_CTRL_TRIG_CHAIN_TO_Field
• CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Field
• CH3_CTRL_TRIG_CHAIN_TO_Field
• CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Field
• CH4_CTRL_TRIG_CHAIN_TO_Field
• CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Field
• CH5_CTRL_TRIG_CHAIN_TO_Field
• CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Field
• CH6_CTRL_TRIG_CHAIN_TO_Field
• CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Field
• CH7_CTRL_TRIG_CHAIN_TO_Field
• CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Field
• CH8_CTRL_TRIG_CHAIN_TO_Field
• CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Field
• CH9_CTRL_TRIG_CHAIN_TO_Field
• CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Field
• CHAN_ABORT_CHAN_ABORT_Field
• FIFO_LEVELS_RAF_LVL_Field
• FIFO_LEVELS_TDF_LVL_Field
• FIFO_LEVELS_WAF_LVL_Field
• INTE0_INTE0_Field
• INTE1_INTE1_Field
• INTF0_INTF0_Field
• INTF1_INTF1_Field
• INTR_INTR_Field
• INTS0_INTS0_Field
• INTS1_INTS1_Field
• MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Field
• N_CHANNELS_N_CHANNELS_Field
• SNIFF_CTRL_DMACH_Field
• TIMER_X_Field
• TIMER_Y_Field

Variables

• DMA_Periph

Description

------------- Registers -- -------------

CH0_CTRL_TRIG_CHAIN_TO_Field

subtype CH0_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH0_CTRL_TRIG_DATA_SIZE_Field

type CH0_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH0_CTRL_TRIG_Register

type CH0_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH0_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH0_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH0_CTRL_TRIG_CHAIN_TO_Field := 16#0#;
   TREQ_SEL       : CH0_CTRL_TRIG_TREQ_SEL_Field :=
                     CH0_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH0_CTRL_TRIG_RING_SIZE_Field

type CH0_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH0_CTRL_TRIG_TREQ_SEL_Field

type CH0_CTRL_TRIG_TREQ_SEL_Field is
   CH0_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH0_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Field

subtype CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Field is HAL.UInt6;

CH0_DBG_CTDREQ_Register

type CH0_DBG_CTDREQ_Register is record
   CH0_DBG_CTDREQ : CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH0_DBG_CTDREQ

Reserved_6_31

CH10_CTRL_TRIG_CHAIN_TO_Field

subtype CH10_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH10_CTRL_TRIG_DATA_SIZE_Field

type CH10_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH10_CTRL_TRIG_Register

type CH10_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH10_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH10_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH10_CTRL_TRIG_CHAIN_TO_Field := 16#A#;
   TREQ_SEL       : CH10_CTRL_TRIG_TREQ_SEL_Field :=
                     CH10_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH10_CTRL_TRIG_RING_SIZE_Field

type CH10_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH10_CTRL_TRIG_TREQ_SEL_Field

type CH10_CTRL_TRIG_TREQ_SEL_Field is
   CH10_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH10_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Field

subtype CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Field is HAL.UInt6;

CH10_DBG_CTDREQ_Register

type CH10_DBG_CTDREQ_Register is record
   CH10_DBG_CTDREQ : CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31   : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH10_DBG_CTDREQ

Reserved_6_31

CH11_CTRL_TRIG_CHAIN_TO_Field

subtype CH11_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH11_CTRL_TRIG_DATA_SIZE_Field

type CH11_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH11_CTRL_TRIG_Register

type CH11_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH11_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH11_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH11_CTRL_TRIG_CHAIN_TO_Field := 16#B#;
   TREQ_SEL       : CH11_CTRL_TRIG_TREQ_SEL_Field :=
                     CH11_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH11_CTRL_TRIG_RING_SIZE_Field

type CH11_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH11_CTRL_TRIG_TREQ_SEL_Field

type CH11_CTRL_TRIG_TREQ_SEL_Field is
   CH11_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH11_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Field

subtype CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Field is HAL.UInt6;

CH11_DBG_CTDREQ_Register

type CH11_DBG_CTDREQ_Register is record
   CH11_DBG_CTDREQ : CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31   : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH11_DBG_CTDREQ

Reserved_6_31

CH1_CTRL_TRIG_CHAIN_TO_Field

subtype CH1_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH1_CTRL_TRIG_DATA_SIZE_Field

type CH1_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH1_CTRL_TRIG_Register

type CH1_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH1_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH1_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH1_CTRL_TRIG_CHAIN_TO_Field := 16#1#;
   TREQ_SEL       : CH1_CTRL_TRIG_TREQ_SEL_Field :=
                     CH1_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH1_CTRL_TRIG_RING_SIZE_Field

type CH1_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH1_CTRL_TRIG_TREQ_SEL_Field

type CH1_CTRL_TRIG_TREQ_SEL_Field is
   CH1_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH1_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Field

subtype CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Field is HAL.UInt6;

CH1_DBG_CTDREQ_Register

type CH1_DBG_CTDREQ_Register is record
   CH1_DBG_CTDREQ : CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH1_DBG_CTDREQ

Reserved_6_31

CH2_CTRL_TRIG_CHAIN_TO_Field

subtype CH2_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH2_CTRL_TRIG_DATA_SIZE_Field

type CH2_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH2_CTRL_TRIG_Register

type CH2_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH2_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH2_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH2_CTRL_TRIG_CHAIN_TO_Field := 16#2#;
   TREQ_SEL       : CH2_CTRL_TRIG_TREQ_SEL_Field :=
                     CH2_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH2_CTRL_TRIG_RING_SIZE_Field

type CH2_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH2_CTRL_TRIG_TREQ_SEL_Field

type CH2_CTRL_TRIG_TREQ_SEL_Field is
   CH2_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH2_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Field

subtype CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Field is HAL.UInt6;

CH2_DBG_CTDREQ_Register

type CH2_DBG_CTDREQ_Register is record
   CH2_DBG_CTDREQ : CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH2_DBG_CTDREQ

Reserved_6_31

CH3_CTRL_TRIG_CHAIN_TO_Field

subtype CH3_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH3_CTRL_TRIG_DATA_SIZE_Field

type CH3_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH3_CTRL_TRIG_Register

type CH3_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH3_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH3_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH3_CTRL_TRIG_CHAIN_TO_Field := 16#3#;
   TREQ_SEL       : CH3_CTRL_TRIG_TREQ_SEL_Field :=
                     CH3_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH3_CTRL_TRIG_RING_SIZE_Field

type CH3_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH3_CTRL_TRIG_TREQ_SEL_Field

type CH3_CTRL_TRIG_TREQ_SEL_Field is
   CH3_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH3_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Field

subtype CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Field is HAL.UInt6;

CH3_DBG_CTDREQ_Register

type CH3_DBG_CTDREQ_Register is record
   CH3_DBG_CTDREQ : CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH3_DBG_CTDREQ

Reserved_6_31

CH4_CTRL_TRIG_CHAIN_TO_Field

subtype CH4_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH4_CTRL_TRIG_DATA_SIZE_Field

type CH4_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH4_CTRL_TRIG_Register

type CH4_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH4_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH4_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH4_CTRL_TRIG_CHAIN_TO_Field := 16#4#;
   TREQ_SEL       : CH4_CTRL_TRIG_TREQ_SEL_Field :=
                     CH4_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH4_CTRL_TRIG_RING_SIZE_Field

type CH4_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH4_CTRL_TRIG_TREQ_SEL_Field

type CH4_CTRL_TRIG_TREQ_SEL_Field is
   CH4_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH4_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Field

subtype CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Field is HAL.UInt6;

CH4_DBG_CTDREQ_Register

type CH4_DBG_CTDREQ_Register is record
   CH4_DBG_CTDREQ : CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH4_DBG_CTDREQ

Reserved_6_31

CH5_CTRL_TRIG_CHAIN_TO_Field

subtype CH5_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH5_CTRL_TRIG_DATA_SIZE_Field

type CH5_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH5_CTRL_TRIG_Register

type CH5_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH5_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH5_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH5_CTRL_TRIG_CHAIN_TO_Field := 16#5#;
   TREQ_SEL       : CH5_CTRL_TRIG_TREQ_SEL_Field :=
                     CH5_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH5_CTRL_TRIG_RING_SIZE_Field

type CH5_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH5_CTRL_TRIG_TREQ_SEL_Field

type CH5_CTRL_TRIG_TREQ_SEL_Field is
   CH5_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH5_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Field

subtype CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Field is HAL.UInt6;

CH5_DBG_CTDREQ_Register

type CH5_DBG_CTDREQ_Register is record
   CH5_DBG_CTDREQ : CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH5_DBG_CTDREQ

Reserved_6_31

CH6_CTRL_TRIG_CHAIN_TO_Field

subtype CH6_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH6_CTRL_TRIG_DATA_SIZE_Field

type CH6_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH6_CTRL_TRIG_Register

type CH6_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH6_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH6_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH6_CTRL_TRIG_CHAIN_TO_Field := 16#6#;
   TREQ_SEL       : CH6_CTRL_TRIG_TREQ_SEL_Field :=
                     CH6_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH6_CTRL_TRIG_RING_SIZE_Field

type CH6_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH6_CTRL_TRIG_TREQ_SEL_Field

type CH6_CTRL_TRIG_TREQ_SEL_Field is
   CH6_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH6_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Field

subtype CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Field is HAL.UInt6;

CH6_DBG_CTDREQ_Register

type CH6_DBG_CTDREQ_Register is record
   CH6_DBG_CTDREQ : CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH6_DBG_CTDREQ

Reserved_6_31

CH7_CTRL_TRIG_CHAIN_TO_Field

subtype CH7_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH7_CTRL_TRIG_DATA_SIZE_Field

type CH7_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH7_CTRL_TRIG_Register

type CH7_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH7_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH7_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH7_CTRL_TRIG_CHAIN_TO_Field := 16#7#;
   TREQ_SEL       : CH7_CTRL_TRIG_TREQ_SEL_Field :=
                     CH7_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH7_CTRL_TRIG_RING_SIZE_Field

type CH7_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH7_CTRL_TRIG_TREQ_SEL_Field

type CH7_CTRL_TRIG_TREQ_SEL_Field is
   CH7_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH7_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Field

subtype CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Field is HAL.UInt6;

CH7_DBG_CTDREQ_Register

type CH7_DBG_CTDREQ_Register is record
   CH7_DBG_CTDREQ : CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH7_DBG_CTDREQ

Reserved_6_31

CH8_CTRL_TRIG_CHAIN_TO_Field

subtype CH8_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH8_CTRL_TRIG_DATA_SIZE_Field

type CH8_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH8_CTRL_TRIG_Register

type CH8_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH8_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH8_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH8_CTRL_TRIG_CHAIN_TO_Field := 16#8#;
   TREQ_SEL       : CH8_CTRL_TRIG_TREQ_SEL_Field :=
                     CH8_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH8_CTRL_TRIG_RING_SIZE_Field

type CH8_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH8_CTRL_TRIG_TREQ_SEL_Field

type CH8_CTRL_TRIG_TREQ_SEL_Field is
   CH8_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH8_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Field

subtype CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Field is HAL.UInt6;

CH8_DBG_CTDREQ_Register

type CH8_DBG_CTDREQ_Register is record
   CH8_DBG_CTDREQ : CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH8_DBG_CTDREQ

Reserved_6_31

CH9_CTRL_TRIG_CHAIN_TO_Field

subtype CH9_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4;

CH9_CTRL_TRIG_DATA_SIZE_Field

type CH9_CTRL_TRIG_DATA_SIZE_Field is
  (SIZE_BYTE,
   SIZE_HALFWORD,
   SIZE_WORD)
  with Size => 2;

Enumeration Literal

SIZE_BYTE

SIZE_HALFWORD

SIZE_WORD

CH9_CTRL_TRIG_Register

type CH9_CTRL_TRIG_Register is record
   EN             : Boolean := False;
   HIGH_PRIORITY  : Boolean := False;
   DATA_SIZE      : CH9_CTRL_TRIG_DATA_SIZE_Field :=
                     RP2040_SVD.DMA.SIZE_BYTE;
   INCR_READ      : Boolean := False;
   INCR_WRITE     : Boolean := False;
   RING_SIZE      : CH9_CTRL_TRIG_RING_SIZE_Field :=
                     RP2040_SVD.DMA.RING_NONE;
   RING_SEL       : Boolean := False;
   CHAIN_TO       : CH9_CTRL_TRIG_CHAIN_TO_Field := 16#9#;
   TREQ_SEL       : CH9_CTRL_TRIG_TREQ_SEL_Field :=
                     CH9_CTRL_TRIG_TREQ_SEL_Field_Reset;
   IRQ_QUIET      : Boolean := False;
   BSWAP          : Boolean := False;
   SNIFF_EN       : Boolean := False;
   BUSY           : Boolean := False;
   Reserved_25_28 : HAL.UInt4 := 16#0#;
   WRITE_ERROR    : Boolean := False;
   READ_ERROR     : Boolean := False;
   AHB_ERROR      : Boolean := False;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

HIGH_PRIORITY

DATA_SIZE

INCR_READ

INCR_WRITE

RING_SIZE

RING_SEL

CHAIN_TO

TREQ_SEL

IRQ_QUIET

BSWAP

SNIFF_EN

BUSY

Reserved_25_28

WRITE_ERROR

READ_ERROR

AHB_ERROR

CH9_CTRL_TRIG_RING_SIZE_Field

type CH9_CTRL_TRIG_RING_SIZE_Field is
  (RING_NONE)
  with Size => 4;

Enumeration Literal

RING_NONE

CH9_CTRL_TRIG_TREQ_SEL_Field

type CH9_CTRL_TRIG_TREQ_SEL_Field is
   CH9_CTRL_TRIG_TREQ_SEL_Field_Reset,
   TIMER0,
   TIMER1,
   TIMER2,
   TIMER3,
   PERMANENT)
  with Size => 6;

Enumeration Literal

CH9_CTRL_TRIG_TREQ_SEL_Field_Reset

Select Timer 0 as TREQ

TIMER0

Select Timer 1 as TREQ

TIMER1

Select Timer 2 as TREQ (Optional)

TIMER2

Select Timer 3 as TREQ (Optional)

TIMER3

Permanent request, for unpaced transfers.

PERMANENT

CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Field

subtype CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Field is HAL.UInt6;

CH9_DBG_CTDREQ_Register

type CH9_DBG_CTDREQ_Register is record
   CH9_DBG_CTDREQ : CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CH9_DBG_CTDREQ

Reserved_6_31

CHAN_ABORT_CHAN_ABORT_Field

subtype CHAN_ABORT_CHAN_ABORT_Field is HAL.UInt16;

CHAN_ABORT_Register

type CHAN_ABORT_Register is record
   CHAN_ABORT     : CHAN_ABORT_CHAN_ABORT_Field := 16#0#;
   Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

CHAN_ABORT

Reserved_16_31

DMA_Periph

DMA_Periph : aliased DMA_Peripheral
  with Import, Address => DMA_Base;

DMA_Peripheral

type DMA_Peripheral is record
   CH0_READ_ADDR             : aliased HAL.UInt32;
   CH0_WRITE_ADDR            : aliased HAL.UInt32;
   CH0_TRANS_COUNT           : aliased HAL.UInt32;
   CH0_CTRL_TRIG             : aliased CH0_CTRL_TRIG_Register;
   CH0_AL1_CTRL              : aliased HAL.UInt32;
   CH0_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH0_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH0_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH0_AL2_CTRL              : aliased HAL.UInt32;
   CH0_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH0_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH0_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH0_AL3_CTRL              : aliased HAL.UInt32;
   CH0_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH0_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH0_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH1_READ_ADDR             : aliased HAL.UInt32;
   CH1_WRITE_ADDR            : aliased HAL.UInt32;
   CH1_TRANS_COUNT           : aliased HAL.UInt32;
   CH1_CTRL_TRIG             : aliased CH1_CTRL_TRIG_Register;
   CH1_AL1_CTRL              : aliased HAL.UInt32;
   CH1_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH1_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH1_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH1_AL2_CTRL              : aliased HAL.UInt32;
   CH1_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH1_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH1_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH1_AL3_CTRL              : aliased HAL.UInt32;
   CH1_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH1_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH1_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH2_READ_ADDR             : aliased HAL.UInt32;
   CH2_WRITE_ADDR            : aliased HAL.UInt32;
   CH2_TRANS_COUNT           : aliased HAL.UInt32;
   CH2_CTRL_TRIG             : aliased CH2_CTRL_TRIG_Register;
   CH2_AL1_CTRL              : aliased HAL.UInt32;
   CH2_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH2_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH2_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH2_AL2_CTRL              : aliased HAL.UInt32;
   CH2_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH2_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH2_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH2_AL3_CTRL              : aliased HAL.UInt32;
   CH2_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH2_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH2_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH3_READ_ADDR             : aliased HAL.UInt32;
   CH3_WRITE_ADDR            : aliased HAL.UInt32;
   CH3_TRANS_COUNT           : aliased HAL.UInt32;
   CH3_CTRL_TRIG             : aliased CH3_CTRL_TRIG_Register;
   CH3_AL1_CTRL              : aliased HAL.UInt32;
   CH3_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH3_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH3_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH3_AL2_CTRL              : aliased HAL.UInt32;
   CH3_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH3_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH3_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH3_AL3_CTRL              : aliased HAL.UInt32;
   CH3_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH3_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH3_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH4_READ_ADDR             : aliased HAL.UInt32;
   CH4_WRITE_ADDR            : aliased HAL.UInt32;
   CH4_TRANS_COUNT           : aliased HAL.UInt32;
   CH4_CTRL_TRIG             : aliased CH4_CTRL_TRIG_Register;
   CH4_AL1_CTRL              : aliased HAL.UInt32;
   CH4_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH4_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH4_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH4_AL2_CTRL              : aliased HAL.UInt32;
   CH4_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH4_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH4_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH4_AL3_CTRL              : aliased HAL.UInt32;
   CH4_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH4_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH4_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH5_READ_ADDR             : aliased HAL.UInt32;
   CH5_WRITE_ADDR            : aliased HAL.UInt32;
   CH5_TRANS_COUNT           : aliased HAL.UInt32;
   CH5_CTRL_TRIG             : aliased CH5_CTRL_TRIG_Register;
   CH5_AL1_CTRL              : aliased HAL.UInt32;
   CH5_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH5_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH5_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH5_AL2_CTRL              : aliased HAL.UInt32;
   CH5_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH5_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH5_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH5_AL3_CTRL              : aliased HAL.UInt32;
   CH5_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH5_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH5_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH6_READ_ADDR             : aliased HAL.UInt32;
   CH6_WRITE_ADDR            : aliased HAL.UInt32;
   CH6_TRANS_COUNT           : aliased HAL.UInt32;
   CH6_CTRL_TRIG             : aliased CH6_CTRL_TRIG_Register;
   CH6_AL1_CTRL              : aliased HAL.UInt32;
   CH6_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH6_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH6_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH6_AL2_CTRL              : aliased HAL.UInt32;
   CH6_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH6_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH6_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH6_AL3_CTRL              : aliased HAL.UInt32;
   CH6_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH6_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH6_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH7_READ_ADDR             : aliased HAL.UInt32;
   CH7_WRITE_ADDR            : aliased HAL.UInt32;
   CH7_TRANS_COUNT           : aliased HAL.UInt32;
   CH7_CTRL_TRIG             : aliased CH7_CTRL_TRIG_Register;
   CH7_AL1_CTRL              : aliased HAL.UInt32;
   CH7_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH7_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH7_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH7_AL2_CTRL              : aliased HAL.UInt32;
   CH7_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH7_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH7_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH7_AL3_CTRL              : aliased HAL.UInt32;
   CH7_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH7_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH7_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH8_READ_ADDR             : aliased HAL.UInt32;
   CH8_WRITE_ADDR            : aliased HAL.UInt32;
   CH8_TRANS_COUNT           : aliased HAL.UInt32;
   CH8_CTRL_TRIG             : aliased CH8_CTRL_TRIG_Register;
   CH8_AL1_CTRL              : aliased HAL.UInt32;
   CH8_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH8_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH8_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH8_AL2_CTRL              : aliased HAL.UInt32;
   CH8_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH8_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH8_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH8_AL3_CTRL              : aliased HAL.UInt32;
   CH8_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH8_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH8_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH9_READ_ADDR             : aliased HAL.UInt32;
   CH9_WRITE_ADDR            : aliased HAL.UInt32;
   CH9_TRANS_COUNT           : aliased HAL.UInt32;
   CH9_CTRL_TRIG             : aliased CH9_CTRL_TRIG_Register;
   CH9_AL1_CTRL              : aliased HAL.UInt32;
   CH9_AL1_READ_ADDR         : aliased HAL.UInt32;
   CH9_AL1_WRITE_ADDR        : aliased HAL.UInt32;
   CH9_AL1_TRANS_COUNT_TRIG  : aliased HAL.UInt32;
   CH9_AL2_CTRL              : aliased HAL.UInt32;
   CH9_AL2_TRANS_COUNT       : aliased HAL.UInt32;
   CH9_AL2_READ_ADDR         : aliased HAL.UInt32;
   CH9_AL2_WRITE_ADDR_TRIG   : aliased HAL.UInt32;
   CH9_AL3_CTRL              : aliased HAL.UInt32;
   CH9_AL3_WRITE_ADDR        : aliased HAL.UInt32;
   CH9_AL3_TRANS_COUNT       : aliased HAL.UInt32;
   CH9_AL3_READ_ADDR_TRIG    : aliased HAL.UInt32;
   CH10_READ_ADDR            : aliased HAL.UInt32;
   CH10_WRITE_ADDR           : aliased HAL.UInt32;
   CH10_TRANS_COUNT          : aliased HAL.UInt32;
   CH10_CTRL_TRIG            : aliased CH10_CTRL_TRIG_Register;
   CH10_AL1_CTRL             : aliased HAL.UInt32;
   CH10_AL1_READ_ADDR        : aliased HAL.UInt32;
   CH10_AL1_WRITE_ADDR       : aliased HAL.UInt32;
   CH10_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32;
   CH10_AL2_CTRL             : aliased HAL.UInt32;
   CH10_AL2_TRANS_COUNT      : aliased HAL.UInt32;
   CH10_AL2_READ_ADDR        : aliased HAL.UInt32;
   CH10_AL2_WRITE_ADDR_TRIG  : aliased HAL.UInt32;
   CH10_AL3_CTRL             : aliased HAL.UInt32;
   CH10_AL3_WRITE_ADDR       : aliased HAL.UInt32;
   CH10_AL3_TRANS_COUNT      : aliased HAL.UInt32;
   CH10_AL3_READ_ADDR_TRIG   : aliased HAL.UInt32;
   CH11_READ_ADDR            : aliased HAL.UInt32;
   CH11_WRITE_ADDR           : aliased HAL.UInt32;
   CH11_TRANS_COUNT          : aliased HAL.UInt32;
   CH11_CTRL_TRIG            : aliased CH11_CTRL_TRIG_Register;
   CH11_AL1_CTRL             : aliased HAL.UInt32;
   CH11_AL1_READ_ADDR        : aliased HAL.UInt32;
   CH11_AL1_WRITE_ADDR       : aliased HAL.UInt32;
   CH11_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32;
   CH11_AL2_CTRL             : aliased HAL.UInt32;
   CH11_AL2_TRANS_COUNT      : aliased HAL.UInt32;
   CH11_AL2_READ_ADDR        : aliased HAL.UInt32;
   CH11_AL2_WRITE_ADDR_TRIG  : aliased HAL.UInt32;
   CH11_AL3_CTRL             : aliased HAL.UInt32;
   CH11_AL3_WRITE_ADDR       : aliased HAL.UInt32;
   CH11_AL3_TRANS_COUNT      : aliased HAL.UInt32;
   CH11_AL3_READ_ADDR_TRIG   : aliased HAL.UInt32;
   INTR                      : aliased INTR_Register;
   INTE0                     : aliased INTE0_Register;
   INTF0                     : aliased INTF0_Register;
   INTS0                     : aliased INTS0_Register;
   INTE1                     : aliased INTE1_Register;
   INTF1                     : aliased INTF1_Register;
   INTS1                     : aliased INTS1_Register;
   TIMER0                    : aliased TIMER_Register;
   TIMER1                    : aliased TIMER_Register;
   TIMER2                    : aliased TIMER_Register;
   TIMER3                    : aliased TIMER_Register;
   MULTI_CHAN_TRIGGER        : aliased MULTI_CHAN_TRIGGER_Register;
   SNIFF_CTRL                : aliased SNIFF_CTRL_Register;
   SNIFF_DATA                : aliased HAL.UInt32;
   FIFO_LEVELS               : aliased FIFO_LEVELS_Register;
   CHAN_ABORT                : aliased CHAN_ABORT_Register;
   N_CHANNELS                : aliased N_CHANNELS_Register;
   CH0_DBG_CTDREQ            : aliased CH0_DBG_CTDREQ_Register;
   CH0_DBG_TCR               : aliased HAL.UInt32;
   CH1_DBG_CTDREQ            : aliased CH1_DBG_CTDREQ_Register;
   CH1_DBG_TCR               : aliased HAL.UInt32;
   CH2_DBG_CTDREQ            : aliased CH2_DBG_CTDREQ_Register;
   CH2_DBG_TCR               : aliased HAL.UInt32;
   CH3_DBG_CTDREQ            : aliased CH3_DBG_CTDREQ_Register;
   CH3_DBG_TCR               : aliased HAL.UInt32;
   CH4_DBG_CTDREQ            : aliased CH4_DBG_CTDREQ_Register;
   CH4_DBG_TCR               : aliased HAL.UInt32;
   CH5_DBG_CTDREQ            : aliased CH5_DBG_CTDREQ_Register;
   CH5_DBG_TCR               : aliased HAL.UInt32;
   CH6_DBG_CTDREQ            : aliased CH6_DBG_CTDREQ_Register;
   CH6_DBG_TCR               : aliased HAL.UInt32;
   CH7_DBG_CTDREQ            : aliased CH7_DBG_CTDREQ_Register;
   CH7_DBG_TCR               : aliased HAL.UInt32;
   CH8_DBG_CTDREQ            : aliased CH8_DBG_CTDREQ_Register;
   CH8_DBG_TCR               : aliased HAL.UInt32;
   CH9_DBG_CTDREQ            : aliased CH9_DBG_CTDREQ_Register;
   CH9_DBG_TCR               : aliased HAL.UInt32;
   CH10_DBG_CTDREQ           : aliased CH10_DBG_CTDREQ_Register;
   CH10_DBG_TCR              : aliased HAL.UInt32;
   CH11_DBG_CTDREQ           : aliased CH11_DBG_CTDREQ_Register;
   CH11_DBG_TCR              : aliased HAL.UInt32;
end record
  with Volatile;

Record fields

CH0_READ_ADDR

CH0_WRITE_ADDR

CH0_TRANS_COUNT

CH0_CTRL_TRIG

CH0_AL1_CTRL

CH0_AL1_READ_ADDR

CH0_AL1_WRITE_ADDR

CH0_AL1_TRANS_COUNT_TRIG

CH0_AL2_CTRL

CH0_AL2_TRANS_COUNT

CH0_AL2_READ_ADDR

CH0_AL2_WRITE_ADDR_TRIG

CH0_AL3_CTRL

CH0_AL3_WRITE_ADDR

CH0_AL3_TRANS_COUNT

CH0_AL3_READ_ADDR_TRIG

CH1_READ_ADDR

CH1_WRITE_ADDR

CH1_TRANS_COUNT

CH1_CTRL_TRIG

CH1_AL1_CTRL

CH1_AL1_READ_ADDR

CH1_AL1_WRITE_ADDR

CH1_AL1_TRANS_COUNT_TRIG

CH1_AL2_CTRL

CH1_AL2_TRANS_COUNT

CH1_AL2_READ_ADDR

CH1_AL2_WRITE_ADDR_TRIG

CH1_AL3_CTRL

CH1_AL3_WRITE_ADDR

CH1_AL3_TRANS_COUNT

CH1_AL3_READ_ADDR_TRIG

CH2_READ_ADDR

CH2_WRITE_ADDR

CH2_TRANS_COUNT

CH2_CTRL_TRIG

CH2_AL1_CTRL

CH2_AL1_READ_ADDR

CH2_AL1_WRITE_ADDR

CH2_AL1_TRANS_COUNT_TRIG

CH2_AL2_CTRL

CH2_AL2_TRANS_COUNT

CH2_AL2_READ_ADDR

CH2_AL2_WRITE_ADDR_TRIG

CH2_AL3_CTRL

CH2_AL3_WRITE_ADDR

CH2_AL3_TRANS_COUNT

CH2_AL3_READ_ADDR_TRIG

CH3_READ_ADDR

CH3_WRITE_ADDR

CH3_TRANS_COUNT

CH3_CTRL_TRIG

CH3_AL1_CTRL

CH3_AL1_READ_ADDR

CH3_AL1_WRITE_ADDR

CH3_AL1_TRANS_COUNT_TRIG

CH3_AL2_CTRL

CH3_AL2_TRANS_COUNT

CH3_AL2_READ_ADDR

CH3_AL2_WRITE_ADDR_TRIG

CH3_AL3_CTRL

CH3_AL3_WRITE_ADDR

CH3_AL3_TRANS_COUNT

CH3_AL3_READ_ADDR_TRIG

CH4_READ_ADDR

CH4_WRITE_ADDR

CH4_TRANS_COUNT

CH4_CTRL_TRIG

CH4_AL1_CTRL

CH4_AL1_READ_ADDR

CH4_AL1_WRITE_ADDR

CH4_AL1_TRANS_COUNT_TRIG

CH4_AL2_CTRL

CH4_AL2_TRANS_COUNT

CH4_AL2_READ_ADDR

CH4_AL2_WRITE_ADDR_TRIG

CH4_AL3_CTRL

CH4_AL3_WRITE_ADDR

CH4_AL3_TRANS_COUNT

CH4_AL3_READ_ADDR_TRIG

CH5_READ_ADDR

CH5_WRITE_ADDR

CH5_TRANS_COUNT

CH5_CTRL_TRIG

CH5_AL1_CTRL

CH5_AL1_READ_ADDR

CH5_AL1_WRITE_ADDR

CH5_AL1_TRANS_COUNT_TRIG

CH5_AL2_CTRL

CH5_AL2_TRANS_COUNT

CH5_AL2_READ_ADDR

CH5_AL2_WRITE_ADDR_TRIG

CH5_AL3_CTRL

CH5_AL3_WRITE_ADDR

CH5_AL3_TRANS_COUNT

CH5_AL3_READ_ADDR_TRIG

CH6_READ_ADDR

CH6_WRITE_ADDR

CH6_TRANS_COUNT

CH6_CTRL_TRIG

CH6_AL1_CTRL

CH6_AL1_READ_ADDR

CH6_AL1_WRITE_ADDR

CH6_AL1_TRANS_COUNT_TRIG

CH6_AL2_CTRL

CH6_AL2_TRANS_COUNT

CH6_AL2_READ_ADDR

CH6_AL2_WRITE_ADDR_TRIG

CH6_AL3_CTRL

CH6_AL3_WRITE_ADDR

CH6_AL3_TRANS_COUNT

CH6_AL3_READ_ADDR_TRIG

CH7_READ_ADDR

CH7_WRITE_ADDR

CH7_TRANS_COUNT

CH7_CTRL_TRIG

CH7_AL1_CTRL

CH7_AL1_READ_ADDR

CH7_AL1_WRITE_ADDR

CH7_AL1_TRANS_COUNT_TRIG

CH7_AL2_CTRL

CH7_AL2_TRANS_COUNT

CH7_AL2_READ_ADDR

CH7_AL2_WRITE_ADDR_TRIG

CH7_AL3_CTRL

CH7_AL3_WRITE_ADDR

CH7_AL3_TRANS_COUNT

CH7_AL3_READ_ADDR_TRIG

CH8_READ_ADDR

CH8_WRITE_ADDR

CH8_TRANS_COUNT

CH8_CTRL_TRIG

CH8_AL1_CTRL

CH8_AL1_READ_ADDR

CH8_AL1_WRITE_ADDR

CH8_AL1_TRANS_COUNT_TRIG

CH8_AL2_CTRL

CH8_AL2_TRANS_COUNT

CH8_AL2_READ_ADDR

CH8_AL2_WRITE_ADDR_TRIG

CH8_AL3_CTRL

CH8_AL3_WRITE_ADDR

CH8_AL3_TRANS_COUNT

CH8_AL3_READ_ADDR_TRIG

CH9_READ_ADDR

CH9_WRITE_ADDR

CH9_TRANS_COUNT

CH9_CTRL_TRIG

CH9_AL1_CTRL

CH9_AL1_READ_ADDR

CH9_AL1_WRITE_ADDR

CH9_AL1_TRANS_COUNT_TRIG

CH9_AL2_CTRL

CH9_AL2_TRANS_COUNT

CH9_AL2_READ_ADDR

CH9_AL2_WRITE_ADDR_TRIG

CH9_AL3_CTRL

CH9_AL3_WRITE_ADDR

CH9_AL3_TRANS_COUNT

CH9_AL3_READ_ADDR_TRIG

CH10_READ_ADDR

CH10_WRITE_ADDR

CH10_TRANS_COUNT

CH10_CTRL_TRIG

CH10_AL1_CTRL

CH10_AL1_READ_ADDR

CH10_AL1_WRITE_ADDR

CH10_AL1_TRANS_COUNT_TRIG

CH10_AL2_CTRL

CH10_AL2_TRANS_COUNT

CH10_AL2_READ_ADDR

CH10_AL2_WRITE_ADDR_TRIG

CH10_AL3_CTRL

CH10_AL3_WRITE_ADDR

CH10_AL3_TRANS_COUNT

CH10_AL3_READ_ADDR_TRIG

CH11_READ_ADDR

CH11_WRITE_ADDR

CH11_TRANS_COUNT

CH11_CTRL_TRIG

CH11_AL1_CTRL

CH11_AL1_READ_ADDR

CH11_AL1_WRITE_ADDR

CH11_AL1_TRANS_COUNT_TRIG

CH11_AL2_CTRL

CH11_AL2_TRANS_COUNT

CH11_AL2_READ_ADDR

CH11_AL2_WRITE_ADDR_TRIG

CH11_AL3_CTRL

CH11_AL3_WRITE_ADDR

CH11_AL3_TRANS_COUNT

CH11_AL3_READ_ADDR_TRIG

INTR

INTE0

INTF0

INTS0

INTE1

INTF1

INTS1

TIMER0

TIMER1

TIMER2

TIMER3

MULTI_CHAN_TRIGGER

SNIFF_CTRL

SNIFF_DATA

FIFO_LEVELS

CHAN_ABORT

N_CHANNELS

CH0_DBG_CTDREQ

CH0_DBG_TCR

CH1_DBG_CTDREQ

CH1_DBG_TCR

CH2_DBG_CTDREQ

CH2_DBG_TCR

CH3_DBG_CTDREQ

CH3_DBG_TCR

CH4_DBG_CTDREQ

CH4_DBG_TCR

CH5_DBG_CTDREQ

CH5_DBG_TCR

CH6_DBG_CTDREQ

CH6_DBG_TCR

CH7_DBG_CTDREQ

CH7_DBG_TCR

CH8_DBG_CTDREQ

CH8_DBG_TCR

CH9_DBG_CTDREQ

CH9_DBG_TCR

CH10_DBG_CTDREQ

CH10_DBG_TCR

CH11_DBG_CTDREQ

CH11_DBG_TCR

FIFO_LEVELS_RAF_LVL_Field

subtype FIFO_LEVELS_RAF_LVL_Field is HAL.UInt8;

FIFO_LEVELS_Register

type FIFO_LEVELS_Register is record
   TDF_LVL        : FIFO_LEVELS_TDF_LVL_Field;
   WAF_LVL        : FIFO_LEVELS_WAF_LVL_Field;
   RAF_LVL        : FIFO_LEVELS_RAF_LVL_Field;
   Reserved_24_31 : HAL.UInt8;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

TDF_LVL

WAF_LVL

RAF_LVL

Reserved_24_31

FIFO_LEVELS_TDF_LVL_Field

subtype FIFO_LEVELS_TDF_LVL_Field is HAL.UInt8;

FIFO_LEVELS_WAF_LVL_Field

subtype FIFO_LEVELS_WAF_LVL_Field is HAL.UInt8;

INTE0_INTE0_Field

subtype INTE0_INTE0_Field is HAL.UInt16;

INTE0_Register

type INTE0_Register is record
   INTE0          : INTE0_INTE0_Field := 16#0#;
   Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTE0

Reserved_16_31

INTE1_INTE1_Field

subtype INTE1_INTE1_Field is HAL.UInt16;

INTE1_Register

type INTE1_Register is record
   INTE1          : INTE1_INTE1_Field := 16#0#;
   Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTE1

Reserved_16_31

INTF0_INTF0_Field

subtype INTF0_INTF0_Field is HAL.UInt16;

INTF0_Register

type INTF0_Register is record
   INTF0          : INTF0_INTF0_Field := 16#0#;
   Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTF0

Reserved_16_31

INTF1_INTF1_Field

subtype INTF1_INTF1_Field is HAL.UInt16;

INTF1_Register

type INTF1_Register is record
   INTF1          : INTF1_INTF1_Field := 16#0#;
   Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTF1

Reserved_16_31

INTR_INTR_Field

subtype INTR_INTR_Field is HAL.UInt16;

INTR_Register

type INTR_Register is record
   INTR           : INTR_INTR_Field;
   Reserved_16_31 : HAL.UInt16;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTR

Reserved_16_31

INTS0_INTS0_Field

subtype INTS0_INTS0_Field is HAL.UInt16;

INTS0_Register

type INTS0_Register is record
   INTS0          : INTS0_INTS0_Field := 16#0#;
   Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTS0

Reserved_16_31

INTS1_INTS1_Field

subtype INTS1_INTS1_Field is HAL.UInt16;

INTS1_Register

type INTS1_Register is record
   INTS1          : INTS1_INTS1_Field := 16#0#;
   Reserved_16_31 : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTS1

Reserved_16_31

MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Field

subtype MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Field is HAL.UInt16;

MULTI_CHAN_TRIGGER_Register

type MULTI_CHAN_TRIGGER_Register is record
   MULTI_CHAN_TRIGGER : MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Field :=
                         16#0#;
   Reserved_16_31     : HAL.UInt16 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

MULTI_CHAN_TRIGGER

Reserved_16_31

N_CHANNELS_N_CHANNELS_Field

subtype N_CHANNELS_N_CHANNELS_Field is HAL.UInt5;

N_CHANNELS_Register

type N_CHANNELS_Register is record
   N_CHANNELS    : N_CHANNELS_N_CHANNELS_Field;
   Reserved_5_31 : HAL.UInt27;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

N_CHANNELS

Reserved_5_31

SNIFF_CTRL_CALC_Field

type SNIFF_CTRL_CALC_Field is
   CRC32,
   CRC32R,
   CRC16,
   CRC16R,
   EVEN,
   SUM)
  with Size => 4;

Enumeration Literal

CRC32

Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data

CRC32R

Calculate a CRC-16-CCITT

CRC16

Calculate a CRC-16-CCITT with bit reversed data

CRC16R

XOR reduction over all data. == 1 if the total 1 population count is odd.

EVEN

Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)

SUM

SNIFF_CTRL_DMACH_Field

subtype SNIFF_CTRL_DMACH_Field is HAL.UInt4;

SNIFF_CTRL_Register

type SNIFF_CTRL_Register is record
   EN             : Boolean := False;
   DMACH          : SNIFF_CTRL_DMACH_Field := 16#0#;
   CALC           : SNIFF_CTRL_CALC_Field := RP2040_SVD.DMA.CRC32;
   BSWAP          : Boolean := False;
   OUT_REV        : Boolean := False;
   OUT_INV        : Boolean := False;
   Reserved_12_31 : HAL.UInt20 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

EN

DMACH

CALC

BSWAP

OUT_REV

OUT_INV

Reserved_12_31

TIMER_Register

type TIMER_Register is record
   Y : TIMER_Y_Field := 16#0#;
   X : TIMER_X_Field := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

Y

X

TIMER_X_Field

subtype TIMER_X_Field is HAL.UInt16;

TIMER_Y_Field

subtype TIMER_Y_Field is HAL.UInt16;