------------- Registers -- -------------
type CTRL_Register is record
EN : Boolean := True;
ERR_BADWRITE : Boolean := True;
Reserved_2_2 : HAL.Bit := 16#0#;
POWER_DOWN : Boolean := False;
Reserved_4_31 : HAL.UInt28 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type FLUSH_Register is record
FLUSH : Boolean := False;
Reserved_1_31 : HAL.UInt31 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type STAT_Register is record
FLUSH_READY : Boolean;
FIFO_EMPTY : Boolean;
FIFO_FULL : Boolean;
Reserved_3_31 : HAL.UInt29;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
type STREAM_ADDR_Register is record
Reserved_0_1 : HAL.UInt2 := 16#0#;
STREAM_ADDR : STREAM_ADDR_STREAM_ADDR_Field := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype STREAM_ADDR_STREAM_ADDR_Field is HAL.UInt30;
type STREAM_CTR_Register is record
STREAM_CTR : STREAM_CTR_STREAM_CTR_Field := 16#0#;
Reserved_22_31 : HAL.UInt10 := 16#0#;
end record
with Volatile_Full_Access, Object_Size => 32,
Bit_Order => System.Low_Order_First;
subtype STREAM_CTR_STREAM_CTR_Field is HAL.UInt22;
XIP_CTRL_Periph : aliased XIP_CTRL_Peripheral
with Import, Address => XIP_CTRL_Base;
type XIP_CTRL_Peripheral is record
CTRL : aliased CTRL_Register;
FLUSH : aliased FLUSH_Register;
STAT : aliased STAT_Register;
CTR_HIT : aliased HAL.UInt32;
CTR_ACC : aliased HAL.UInt32;
STREAM_ADDR : aliased STREAM_ADDR_Register;
STREAM_CTR : aliased STREAM_CTR_Register;
STREAM_FIFO : aliased HAL.UInt32;
end record
with Volatile;