RP.DMA

Entities

Simple Types

Record Types

Subtypes

Subprograms

Description

Ack_IRQ

procedure Ack_IRQ (Channel : DMA_Channel_Id;
                   IRQ     : DMA_IRQ_Id)
Parameters
Channel
IRQ

Busy

function Busy
   (Channel : DMA_Channel_Id)
   return Boolean
Parameters
Channel
Return Value

Checksum

function Checksum
   return HAL.UInt32
Return Value

Checksum_Algorithm

type Checksum_Algorithm is
   (CRC_32,
    CRC_32R,
    CRC_16,
    CRC_16R,
    EVEN,
    SUM);
Enumeration Literal
CRC_32

CRC-32 (IEEE802.3 polynomial)

CRC_32R

CRC-32 (IEEE802.3 polynomial) with bit reversed data

CRC_16

CRC-16-CCITT

CRC_16R

CRC-16-CCITT with bit reversed data

EVEN

XOR reduction over all data. == 1 if total 1 population count is odd

SUM

Calculate a simple 32-bit checksum (addition with 32 bit accumulator)

Configure

procedure Configure
   (Channel : DMA_Channel_Id;
    Config  : DMA_Configuration)
Parameters
Channel
Config

Disable

procedure Disable
   (Channel : DMA_Channel_Id)
Parameters
Channel

Disable_IRQ

procedure Disable_IRQ (Channel : DMA_Channel_Id;
                       IRQ     : DMA_IRQ_Id)
Parameters
Channel
IRQ

DMA_Channel_Id

type DMA_Channel_Id is range 0 .. 11
   with Size => 4;

DMA_Configuration

type DMA_Configuration is record
   High_Priority   : Boolean := False;
   Data_Size       : Transfer_Width := Transfer_8;
   Increment_Read  : Boolean := False;
   Increment_Write : Boolean := False;
   Ring_Size       : HAL.UInt4 := 0;
   Ring_Wrap       : Ring_Wrap_Select := Wrap_Read;
   Chain_To        : DMA_Channel_Id := 0;
   Trigger         : DMA_Request_Trigger := PERMANENT;
   Quiet           : Boolean := False;
   Byte_Swap       : Boolean := False;
   Sniff           : Boolean := False;
end record;
Record fields
High_Priority

Schedule this channel before others

Data_Size

Bits per transfer (byte, halfword, word)

Increment_Read

Increment read address after transfer

Increment_Write

Increment write address after transfer

Ring_Size

Ring buffer size

Ring_Wrap

Read or write buffer is a ring buffer

Chain_To

Trigger another channel after transfer.

Trigger

Trigger a transfer on this signal

Quiet

Disable interrupts

Byte_Swap

Reverse byte order

Sniff

Send data to sniff checksum

DMA_IRQ_Id

subtype DMA_IRQ_Id is Natural range 0 .. 1;

DMA_Request_Trigger

type DMA_Request_Trigger is
   (PIO0_TX0, PIO0_TX1, PIO0_TX2, PIO0_TX3, PIO0_RX0, PIO0_RX1, PIO0_RX2, PIO0_RX3,
    PIO1_TX0, PIO1_TX1, PIO1_TX2, PIO1_TX3, PIO1_RX0, PIO1_RX1, PIO1_RX2, PIO1_RX3,
    SPI0_TX, SPI0_RX,
    SPI1_TX, SPI1_RX,
    UART0_TX, UART0_RX,
    UART1_TX, UART1_RX,
    PWM_WRAP0, PWM_WRAP1, PWM_WRAP2, PWM_WRAP3, PWM_WRAP4, PWM_WRAP5, PWM_WRAP6, PWM_WRAP7,
    I2C0_TX, I2C0_RX,
    I2C1_TX, I2C1_RX,
    ADC,
    XIP_STREAM, XIP_SSITX, XIP_SSIRX,
    TIMER0, TIMER1, TIMER2, TIMER3,
    PERMANENT)
    with Size => 6;
Enumeration Literal
PIO0_TX0
PIO0_TX1
PIO0_TX2
PIO0_TX3
PIO0_RX0
PIO0_RX1
PIO0_RX2
PIO0_RX3
PIO1_TX0
PIO1_TX1
PIO1_TX2
PIO1_TX3
PIO1_RX0
PIO1_RX1
PIO1_RX2
PIO1_RX3
SPI0_TX
SPI0_RX
SPI1_TX
SPI1_RX
UART0_TX
UART0_RX
UART1_TX
UART1_RX
PWM_WRAP0
PWM_WRAP1
PWM_WRAP2
PWM_WRAP3
PWM_WRAP4
PWM_WRAP5
PWM_WRAP6
PWM_WRAP7
I2C0_TX
I2C0_RX
I2C1_TX
I2C1_RX
ADC
XIP_STREAM
XIP_SSITX
XIP_SSIRX
TIMER0
TIMER1
TIMER2
TIMER3
PERMANENT

DMA_Status

type DMA_Status is record
   Enabled             : Boolean := False;
   Busy                : Boolean := False;
   Write_Error         : Boolean := False;
   Read_Error          : Boolean := False;
   AHB_Error           : Boolean := False;
   Transfers_Remaining : Natural := 0;
end record;
Record fields
Enabled
Busy
Write_Error
Read_Error
AHB_Error
Transfers_Remaining

DMA_Timer_Id

subtype DMA_Timer_Id is DMA_Request_Trigger range TIMER0 .. TIMER3;

Enable

procedure Enable

Enable_Checksum

procedure Enable_Checksum
   (Channel   : DMA_Channel_Id;
    Algorithm : Checksum_Algorithm;
    Byte_Swap : Boolean := False;
    Reversed  : Boolean := False;
    Inverted  : Boolean := False)
Parameters
Channel
Algorithm
Byte_Swap
Reversed
Inverted

Enable_IRQ

procedure Enable_IRQ (Channel : DMA_Channel_Id;
                      IRQ     : DMA_IRQ_Id)
Parameters
Channel
IRQ

IRQ_Status

function IRQ_Status (Channel : DMA_Channel_Id;
                     IRQ     : DMA_IRQ_Id)
                     return Boolean

Return True if the IRQ is triggered

Parameters
Channel
IRQ
Return Value

Ring_Wrap_Select

type Ring_Wrap_Select is (Wrap_Read, Wrap_Write)
   with Size => 1;
Enumeration Literal
Wrap_Read
Wrap_Write

Set_Checksum

procedure Set_Checksum
   (Value : HAL.UInt32)
Parameters
Value

Set_Pacing_Timer

procedure Set_Pacing_Timer
   (Timer : DMA_Timer_Id;
    X, Y  : HAL.UInt16)

The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

Parameters
Timer
X
Y

Setup

procedure Setup
   (Channel  : DMA_Channel_Id;
    From, To : System.Address;
    Count    : HAL.UInt32)
Parameters
Channel
From
To
Count

Start

procedure Start
   (Channel : DMA_Channel_Id)

Setup must be called before Start. If you call Start more than once and Increment_Read or Increment_Write are True, these pointers are *not* reset to their initial Setup values, unless you've configured the channel with Ring_Wrap and Ring_Size.

Parameters
Channel

Start

procedure Start
   (Channel  : DMA_Channel_Id;
    From, To : System.Address;
    Count    : HAL.UInt32)

This version of Start performs the Setup for you.

Parameters
Channel
From
To
Count

Status

function Status
   (Channel : DMA_Channel_Id)
   return DMA_Status
Parameters
Channel
Return Value

Transfer_Width

type Transfer_Width is (Transfer_8, Transfer_16, Transfer_32)
   with Size => 2;
Enumeration Literal
Transfer_8
Transfer_16
Transfer_32