RP2040_SVD.SIO

Entities

Array Types

• INTERP0_CTRL_LANE0_OVERF_Field_Array
• INTERP1_CTRL_LANE0_OVERF_Field_Array

Record Types

• DIV_CSR_Register
• FIFO_ST_Register
• GPIO_HI_IN_Register
• GPIO_HI_OE_CLR_Register
• GPIO_HI_OE_Register
• GPIO_HI_OE_SET_Register
• GPIO_HI_OE_XOR_Register
• GPIO_HI_OUT_CLR_Register
• GPIO_HI_OUT_Register
• GPIO_HI_OUT_SET_Register
• GPIO_HI_OUT_XOR_Register
• GPIO_IN_Register
• GPIO_OE_CLR_Register
• GPIO_OE_Register
• GPIO_OE_SET_Register
• GPIO_OE_XOR_Register
• GPIO_OUT_CLR_Register
• GPIO_OUT_Register
• GPIO_OUT_SET_Register
• GPIO_OUT_XOR_Register
• INTERP0_ACCUM0_ADD_Register
• INTERP0_ACCUM1_ADD_Register
• INTERP0_CTRL_LANE0_OVERF_Field
• INTERP0_CTRL_LANE0_Register
• INTERP0_CTRL_LANE1_Register
• INTERP1_ACCUM0_ADD_Register
• INTERP1_ACCUM1_ADD_Register
• INTERP1_CTRL_LANE0_OVERF_Field
• INTERP1_CTRL_LANE0_Register
• INTERP1_CTRL_LANE1_Register
• SIO_Peripheral

Subtypes

• GPIO_HI_IN_GPIO_HI_IN_Field
• GPIO_HI_OE_CLR_GPIO_HI_OE_CLR_Field
• GPIO_HI_OE_GPIO_HI_OE_Field
• GPIO_HI_OE_SET_GPIO_HI_OE_SET_Field
• GPIO_HI_OE_XOR_GPIO_HI_OE_XOR_Field
• GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR_Field
• GPIO_HI_OUT_GPIO_HI_OUT_Field
• GPIO_HI_OUT_SET_GPIO_HI_OUT_SET_Field
• GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR_Field
• GPIO_IN_GPIO_IN_Field
• GPIO_OE_CLR_GPIO_OE_CLR_Field
• GPIO_OE_GPIO_OE_Field
• GPIO_OE_SET_GPIO_OE_SET_Field
• GPIO_OE_XOR_GPIO_OE_XOR_Field
• GPIO_OUT_CLR_GPIO_OUT_CLR_Field
• GPIO_OUT_GPIO_OUT_Field
• GPIO_OUT_SET_GPIO_OUT_SET_Field
• GPIO_OUT_XOR_GPIO_OUT_XOR_Field
• INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field
• INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field
• INTERP0_CTRL_LANE0_FORCE_MSB_Field
• INTERP0_CTRL_LANE0_MASK_LSB_Field
• INTERP0_CTRL_LANE0_MASK_MSB_Field
• INTERP0_CTRL_LANE0_SHIFT_Field
• INTERP0_CTRL_LANE1_FORCE_MSB_Field
• INTERP0_CTRL_LANE1_MASK_LSB_Field
• INTERP0_CTRL_LANE1_MASK_MSB_Field
• INTERP0_CTRL_LANE1_SHIFT_Field
• INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field
• INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field
• INTERP1_CTRL_LANE0_FORCE_MSB_Field
• INTERP1_CTRL_LANE0_MASK_LSB_Field
• INTERP1_CTRL_LANE0_MASK_MSB_Field
• INTERP1_CTRL_LANE0_SHIFT_Field
• INTERP1_CTRL_LANE1_FORCE_MSB_Field
• INTERP1_CTRL_LANE1_MASK_LSB_Field
• INTERP1_CTRL_LANE1_MASK_MSB_Field
• INTERP1_CTRL_LANE1_SHIFT_Field

Variables

• SIO_Periph

Description

------------- Registers -- -------------

DIV_CSR_Register

type DIV_CSR_Register is record
   READY         : Boolean;
   DIRTY         : Boolean;
   Reserved_2_31 : HAL.UInt30;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

READY

DIRTY

Reserved_2_31

FIFO_ST_Register

type FIFO_ST_Register is record
   VLD           : Boolean := False;
   RDY           : Boolean := True;
   WOF           : Boolean := False;
   ROE           : Boolean := False;
   Reserved_4_31 : HAL.UInt28 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

VLD

RDY

WOF

ROE

Reserved_4_31

GPIO_HI_IN_GPIO_HI_IN_Field

subtype GPIO_HI_IN_GPIO_HI_IN_Field is HAL.UInt6;

GPIO_HI_IN_Register

type GPIO_HI_IN_Register is record
   GPIO_HI_IN    : GPIO_HI_IN_GPIO_HI_IN_Field;
   Reserved_6_31 : HAL.UInt26;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_IN

Reserved_6_31

GPIO_HI_OE_CLR_GPIO_HI_OE_CLR_Field

subtype GPIO_HI_OE_CLR_GPIO_HI_OE_CLR_Field is HAL.UInt6;

GPIO_HI_OE_CLR_Register

type GPIO_HI_OE_CLR_Register is record
   GPIO_HI_OE_CLR : GPIO_HI_OE_CLR_GPIO_HI_OE_CLR_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OE_CLR

Reserved_6_31

GPIO_HI_OE_GPIO_HI_OE_Field

subtype GPIO_HI_OE_GPIO_HI_OE_Field is HAL.UInt6;

GPIO_HI_OE_Register

type GPIO_HI_OE_Register is record
   GPIO_HI_OE    : GPIO_HI_OE_GPIO_HI_OE_Field := 16#0#;
   Reserved_6_31 : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OE

Reserved_6_31

GPIO_HI_OE_SET_GPIO_HI_OE_SET_Field

subtype GPIO_HI_OE_SET_GPIO_HI_OE_SET_Field is HAL.UInt6;

GPIO_HI_OE_SET_Register

type GPIO_HI_OE_SET_Register is record
   GPIO_HI_OE_SET : GPIO_HI_OE_SET_GPIO_HI_OE_SET_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OE_SET

Reserved_6_31

GPIO_HI_OE_XOR_GPIO_HI_OE_XOR_Field

subtype GPIO_HI_OE_XOR_GPIO_HI_OE_XOR_Field is HAL.UInt6;

GPIO_HI_OE_XOR_Register

type GPIO_HI_OE_XOR_Register is record
   GPIO_HI_OE_XOR : GPIO_HI_OE_XOR_GPIO_HI_OE_XOR_Field := 16#0#;
   Reserved_6_31  : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OE_XOR

Reserved_6_31

GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR_Field

subtype GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR_Field is HAL.UInt6;

GPIO_HI_OUT_CLR_Register

type GPIO_HI_OUT_CLR_Register is record
   GPIO_HI_OUT_CLR : GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR_Field := 16#0#;
   Reserved_6_31   : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OUT_CLR

Reserved_6_31

GPIO_HI_OUT_GPIO_HI_OUT_Field

subtype GPIO_HI_OUT_GPIO_HI_OUT_Field is HAL.UInt6;

GPIO_HI_OUT_Register

type GPIO_HI_OUT_Register is record
   GPIO_HI_OUT   : GPIO_HI_OUT_GPIO_HI_OUT_Field := 16#0#;
   Reserved_6_31 : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OUT

Reserved_6_31

GPIO_HI_OUT_SET_GPIO_HI_OUT_SET_Field

subtype GPIO_HI_OUT_SET_GPIO_HI_OUT_SET_Field is HAL.UInt6;

GPIO_HI_OUT_SET_Register

type GPIO_HI_OUT_SET_Register is record
   GPIO_HI_OUT_SET : GPIO_HI_OUT_SET_GPIO_HI_OUT_SET_Field := 16#0#;
   Reserved_6_31   : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OUT_SET

Reserved_6_31

GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR_Field

subtype GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR_Field is HAL.UInt6;

GPIO_HI_OUT_XOR_Register

type GPIO_HI_OUT_XOR_Register is record
   GPIO_HI_OUT_XOR : GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR_Field := 16#0#;
   Reserved_6_31   : HAL.UInt26 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_HI_OUT_XOR

Reserved_6_31

GPIO_IN_GPIO_IN_Field

subtype GPIO_IN_GPIO_IN_Field is HAL.UInt30;

GPIO_IN_Register

type GPIO_IN_Register is record
   GPIO_IN        : GPIO_IN_GPIO_IN_Field;
   Reserved_30_31 : HAL.UInt2;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_IN

Reserved_30_31

GPIO_OE_CLR_GPIO_OE_CLR_Field

subtype GPIO_OE_CLR_GPIO_OE_CLR_Field is HAL.UInt30;

GPIO_OE_CLR_Register

type GPIO_OE_CLR_Register is record
   GPIO_OE_CLR    : GPIO_OE_CLR_GPIO_OE_CLR_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OE_CLR

Reserved_30_31

GPIO_OE_GPIO_OE_Field

subtype GPIO_OE_GPIO_OE_Field is HAL.UInt30;

GPIO_OE_Register

type GPIO_OE_Register is record
   GPIO_OE        : GPIO_OE_GPIO_OE_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OE

Reserved_30_31

GPIO_OE_SET_GPIO_OE_SET_Field

subtype GPIO_OE_SET_GPIO_OE_SET_Field is HAL.UInt30;

GPIO_OE_SET_Register

type GPIO_OE_SET_Register is record
   GPIO_OE_SET    : GPIO_OE_SET_GPIO_OE_SET_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OE_SET

Reserved_30_31

GPIO_OE_XOR_GPIO_OE_XOR_Field

subtype GPIO_OE_XOR_GPIO_OE_XOR_Field is HAL.UInt30;

GPIO_OE_XOR_Register

type GPIO_OE_XOR_Register is record
   GPIO_OE_XOR    : GPIO_OE_XOR_GPIO_OE_XOR_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OE_XOR

Reserved_30_31

GPIO_OUT_CLR_GPIO_OUT_CLR_Field

subtype GPIO_OUT_CLR_GPIO_OUT_CLR_Field is HAL.UInt30;

GPIO_OUT_CLR_Register

type GPIO_OUT_CLR_Register is record
   GPIO_OUT_CLR   : GPIO_OUT_CLR_GPIO_OUT_CLR_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OUT_CLR

Reserved_30_31

GPIO_OUT_GPIO_OUT_Field

subtype GPIO_OUT_GPIO_OUT_Field is HAL.UInt30;

GPIO_OUT_Register

type GPIO_OUT_Register is record
   GPIO_OUT       : GPIO_OUT_GPIO_OUT_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OUT

Reserved_30_31

GPIO_OUT_SET_GPIO_OUT_SET_Field

subtype GPIO_OUT_SET_GPIO_OUT_SET_Field is HAL.UInt30;

GPIO_OUT_SET_Register

type GPIO_OUT_SET_Register is record
   GPIO_OUT_SET   : GPIO_OUT_SET_GPIO_OUT_SET_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OUT_SET

Reserved_30_31

GPIO_OUT_XOR_GPIO_OUT_XOR_Field

subtype GPIO_OUT_XOR_GPIO_OUT_XOR_Field is HAL.UInt30;

GPIO_OUT_XOR_Register

type GPIO_OUT_XOR_Register is record
   GPIO_OUT_XOR   : GPIO_OUT_XOR_GPIO_OUT_XOR_Field := 16#0#;
   Reserved_30_31 : HAL.UInt2 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

GPIO_OUT_XOR

Reserved_30_31

INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field

subtype INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field is HAL.UInt24;

INTERP0_ACCUM0_ADD_Register

type INTERP0_ACCUM0_ADD_Register is record
   INTERP0_ACCUM0_ADD : INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field :=
                         16#0#;
   Reserved_24_31     : HAL.UInt8 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTERP0_ACCUM0_ADD

Reserved_24_31

INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field

subtype INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field is HAL.UInt24;

INTERP0_ACCUM1_ADD_Register

type INTERP0_ACCUM1_ADD_Register is record
   INTERP0_ACCUM1_ADD : INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field :=
                         16#0#;
   Reserved_24_31     : HAL.UInt8 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTERP0_ACCUM1_ADD

Reserved_24_31

INTERP0_CTRL_LANE0_FORCE_MSB_Field

subtype INTERP0_CTRL_LANE0_FORCE_MSB_Field is HAL.UInt2;

INTERP0_CTRL_LANE0_MASK_LSB_Field

subtype INTERP0_CTRL_LANE0_MASK_LSB_Field is HAL.UInt5;

INTERP0_CTRL_LANE0_MASK_MSB_Field

subtype INTERP0_CTRL_LANE0_MASK_MSB_Field is HAL.UInt5;

INTERP0_CTRL_LANE0_OVERF_Field

type INTERP0_CTRL_LANE0_OVERF_Field
  (As_Array : Boolean := False)
is record
   case As_Array is
      when False =>
         Val : HAL.UInt3;
      when True =>
         Arr : INTERP0_CTRL_LANE0_OVERF_Field_Array;
   end case;
end record
  with Unchecked_Union, Size => 3;

Record fields

As_Array

Val

Arr

INTERP0_CTRL_LANE0_OVERF_Field_Array

type INTERP0_CTRL_LANE0_OVERF_Field_Array is array (0 .. 2) of Boolean
  with Component_Size => 1, Size => 3;

INTERP0_CTRL_LANE0_Register

type INTERP0_CTRL_LANE0_Register is record
   SHIFT          : INTERP0_CTRL_LANE0_SHIFT_Field := 16#0#;
   MASK_LSB       : INTERP0_CTRL_LANE0_MASK_LSB_Field := 16#0#;
   MASK_MSB       : INTERP0_CTRL_LANE0_MASK_MSB_Field := 16#0#;
   SIGNED         : Boolean := False;
   CROSS_INPUT    : Boolean := False;
   CROSS_RESULT   : Boolean := False;
   ADD_RAW        : Boolean := False;
   FORCE_MSB      : INTERP0_CTRL_LANE0_FORCE_MSB_Field := 16#0#;
   BLEND          : Boolean := False;
   Reserved_22_22 : HAL.Bit := 16#0#;
   OVERF          : INTERP0_CTRL_LANE0_OVERF_Field :=
                     (As_Array => False, Val => 16#0#);
   Reserved_26_31 : HAL.UInt6 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

SHIFT

MASK_LSB

MASK_MSB

SIGNED

CROSS_INPUT

CROSS_RESULT

ADD_RAW

FORCE_MSB

BLEND

Reserved_22_22

OVERF

Reserved_26_31

INTERP0_CTRL_LANE0_SHIFT_Field

subtype INTERP0_CTRL_LANE0_SHIFT_Field is HAL.UInt5;

INTERP0_CTRL_LANE1_FORCE_MSB_Field

subtype INTERP0_CTRL_LANE1_FORCE_MSB_Field is HAL.UInt2;

INTERP0_CTRL_LANE1_MASK_LSB_Field

subtype INTERP0_CTRL_LANE1_MASK_LSB_Field is HAL.UInt5;

INTERP0_CTRL_LANE1_MASK_MSB_Field

subtype INTERP0_CTRL_LANE1_MASK_MSB_Field is HAL.UInt5;

INTERP0_CTRL_LANE1_Register

type INTERP0_CTRL_LANE1_Register is record
   SHIFT          : INTERP0_CTRL_LANE1_SHIFT_Field := 16#0#;
   MASK_LSB       : INTERP0_CTRL_LANE1_MASK_LSB_Field := 16#0#;
   MASK_MSB       : INTERP0_CTRL_LANE1_MASK_MSB_Field := 16#0#;
   SIGNED         : Boolean := False;
   CROSS_INPUT    : Boolean := False;
   CROSS_RESULT   : Boolean := False;
   ADD_RAW        : Boolean := False;
   FORCE_MSB      : INTERP0_CTRL_LANE1_FORCE_MSB_Field := 16#0#;
   Reserved_21_31 : HAL.UInt11 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

SHIFT

MASK_LSB

MASK_MSB

SIGNED

CROSS_INPUT

CROSS_RESULT

ADD_RAW

FORCE_MSB

Reserved_21_31

INTERP0_CTRL_LANE1_SHIFT_Field

subtype INTERP0_CTRL_LANE1_SHIFT_Field is HAL.UInt5;

INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field

subtype INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field is HAL.UInt24;

INTERP1_ACCUM0_ADD_Register

type INTERP1_ACCUM0_ADD_Register is record
   INTERP1_ACCUM0_ADD : INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field :=
                         16#0#;
   Reserved_24_31     : HAL.UInt8 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTERP1_ACCUM0_ADD

Reserved_24_31

INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field

subtype INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field is HAL.UInt24;

INTERP1_ACCUM1_ADD_Register

type INTERP1_ACCUM1_ADD_Register is record
   INTERP1_ACCUM1_ADD : INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field :=
                         16#0#;
   Reserved_24_31     : HAL.UInt8 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

INTERP1_ACCUM1_ADD

Reserved_24_31

INTERP1_CTRL_LANE0_FORCE_MSB_Field

subtype INTERP1_CTRL_LANE0_FORCE_MSB_Field is HAL.UInt2;

INTERP1_CTRL_LANE0_MASK_LSB_Field

subtype INTERP1_CTRL_LANE0_MASK_LSB_Field is HAL.UInt5;

INTERP1_CTRL_LANE0_MASK_MSB_Field

subtype INTERP1_CTRL_LANE0_MASK_MSB_Field is HAL.UInt5;

INTERP1_CTRL_LANE0_OVERF_Field

type INTERP1_CTRL_LANE0_OVERF_Field
  (As_Array : Boolean := False)
is record
   case As_Array is
      when False =>
         Val : HAL.UInt3;
      when True =>
         Arr : INTERP1_CTRL_LANE0_OVERF_Field_Array;
   end case;
end record
  with Unchecked_Union, Size => 3;

Record fields

As_Array

Val

Arr

INTERP1_CTRL_LANE0_OVERF_Field_Array

type INTERP1_CTRL_LANE0_OVERF_Field_Array is array (0 .. 2) of Boolean
  with Component_Size => 1, Size => 3;

INTERP1_CTRL_LANE0_Register

type INTERP1_CTRL_LANE0_Register is record
   SHIFT          : INTERP1_CTRL_LANE0_SHIFT_Field := 16#0#;
   MASK_LSB       : INTERP1_CTRL_LANE0_MASK_LSB_Field := 16#0#;
   MASK_MSB       : INTERP1_CTRL_LANE0_MASK_MSB_Field := 16#0#;
   SIGNED         : Boolean := False;
   CROSS_INPUT    : Boolean := False;
   CROSS_RESULT   : Boolean := False;
   ADD_RAW        : Boolean := False;
   FORCE_MSB      : INTERP1_CTRL_LANE0_FORCE_MSB_Field := 16#0#;
   Reserved_21_21 : HAL.Bit := 16#0#;
   CLAMP          : Boolean := False;
   OVERF          : INTERP1_CTRL_LANE0_OVERF_Field :=
                     (As_Array => False, Val => 16#0#);
   Reserved_26_31 : HAL.UInt6 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

SHIFT

MASK_LSB

MASK_MSB

SIGNED

CROSS_INPUT

CROSS_RESULT

ADD_RAW

FORCE_MSB

Reserved_21_21

CLAMP

OVERF

Reserved_26_31

INTERP1_CTRL_LANE0_SHIFT_Field

subtype INTERP1_CTRL_LANE0_SHIFT_Field is HAL.UInt5;

INTERP1_CTRL_LANE1_FORCE_MSB_Field

subtype INTERP1_CTRL_LANE1_FORCE_MSB_Field is HAL.UInt2;

INTERP1_CTRL_LANE1_MASK_LSB_Field

subtype INTERP1_CTRL_LANE1_MASK_LSB_Field is HAL.UInt5;

INTERP1_CTRL_LANE1_MASK_MSB_Field

subtype INTERP1_CTRL_LANE1_MASK_MSB_Field is HAL.UInt5;

INTERP1_CTRL_LANE1_Register

type INTERP1_CTRL_LANE1_Register is record
   SHIFT          : INTERP1_CTRL_LANE1_SHIFT_Field := 16#0#;
   MASK_LSB       : INTERP1_CTRL_LANE1_MASK_LSB_Field := 16#0#;
   MASK_MSB       : INTERP1_CTRL_LANE1_MASK_MSB_Field := 16#0#;
   SIGNED         : Boolean := False;
   CROSS_INPUT    : Boolean := False;
   CROSS_RESULT   : Boolean := False;
   ADD_RAW        : Boolean := False;
   FORCE_MSB      : INTERP1_CTRL_LANE1_FORCE_MSB_Field := 16#0#;
   Reserved_21_31 : HAL.UInt11 := 16#0#;
end record
  with Volatile_Full_Access, Object_Size => 32,
       Bit_Order => System.Low_Order_First;

Record fields

SHIFT

MASK_LSB

MASK_MSB

SIGNED

CROSS_INPUT

CROSS_RESULT

ADD_RAW

FORCE_MSB

Reserved_21_31

INTERP1_CTRL_LANE1_SHIFT_Field

subtype INTERP1_CTRL_LANE1_SHIFT_Field is HAL.UInt5;

SIO_Periph

SIO_Periph : aliased SIO_Peripheral
  with Import, Address => SIO_Base;

SIO_Peripheral

type SIO_Peripheral is record
   CPUID              : aliased HAL.UInt32;
   GPIO_IN            : aliased GPIO_IN_Register;
   GPIO_HI_IN         : aliased GPIO_HI_IN_Register;
   GPIO_OUT           : aliased GPIO_OUT_Register;
   GPIO_OUT_SET       : aliased GPIO_OUT_SET_Register;
   GPIO_OUT_CLR       : aliased GPIO_OUT_CLR_Register;
   GPIO_OUT_XOR       : aliased GPIO_OUT_XOR_Register;
   GPIO_OE            : aliased GPIO_OE_Register;
   GPIO_OE_SET        : aliased GPIO_OE_SET_Register;
   GPIO_OE_CLR        : aliased GPIO_OE_CLR_Register;
   GPIO_OE_XOR        : aliased GPIO_OE_XOR_Register;
   GPIO_HI_OUT        : aliased GPIO_HI_OUT_Register;
   GPIO_HI_OUT_SET    : aliased GPIO_HI_OUT_SET_Register;
   GPIO_HI_OUT_CLR    : aliased GPIO_HI_OUT_CLR_Register;
   GPIO_HI_OUT_XOR    : aliased GPIO_HI_OUT_XOR_Register;
   GPIO_HI_OE         : aliased GPIO_HI_OE_Register;
   GPIO_HI_OE_SET     : aliased GPIO_HI_OE_SET_Register;
   GPIO_HI_OE_CLR     : aliased GPIO_HI_OE_CLR_Register;
   GPIO_HI_OE_XOR     : aliased GPIO_HI_OE_XOR_Register;
   FIFO_ST            : aliased FIFO_ST_Register;
   FIFO_WR            : aliased HAL.UInt32;
   FIFO_RD            : aliased HAL.UInt32;
   SPINLOCK_ST        : aliased HAL.UInt32;
   DIV_UDIVIDEND      : aliased HAL.UInt32;
   DIV_UDIVISOR       : aliased HAL.UInt32;
   DIV_SDIVIDEND      : aliased HAL.UInt32;
   DIV_SDIVISOR       : aliased HAL.UInt32;
   DIV_QUOTIENT       : aliased HAL.UInt32;
   DIV_REMAINDER      : aliased HAL.UInt32;
   DIV_CSR            : aliased DIV_CSR_Register;
   INTERP0_ACCUM0     : aliased HAL.UInt32;
   INTERP0_ACCUM1     : aliased HAL.UInt32;
   INTERP0_BASE0      : aliased HAL.UInt32;
   INTERP0_BASE1      : aliased HAL.UInt32;
   INTERP0_BASE2      : aliased HAL.UInt32;
   INTERP0_POP_LANE0  : aliased HAL.UInt32;
   INTERP0_POP_LANE1  : aliased HAL.UInt32;
   INTERP0_POP_FULL   : aliased HAL.UInt32;
   INTERP0_PEEK_LANE0 : aliased HAL.UInt32;
   INTERP0_PEEK_LANE1 : aliased HAL.UInt32;
   INTERP0_PEEK_FULL  : aliased HAL.UInt32;
   INTERP0_CTRL_LANE0 : aliased INTERP0_CTRL_LANE0_Register;
   INTERP0_CTRL_LANE1 : aliased INTERP0_CTRL_LANE1_Register;
   INTERP0_ACCUM0_ADD : aliased INTERP0_ACCUM0_ADD_Register;
   INTERP0_ACCUM1_ADD : aliased INTERP0_ACCUM1_ADD_Register;
   INTERP0_BASE_1AND0 : aliased HAL.UInt32;
   INTERP1_ACCUM0     : aliased HAL.UInt32;
   INTERP1_ACCUM1     : aliased HAL.UInt32;
   INTERP1_BASE0      : aliased HAL.UInt32;
   INTERP1_BASE1      : aliased HAL.UInt32;
   INTERP1_BASE2      : aliased HAL.UInt32;
   INTERP1_POP_LANE0  : aliased HAL.UInt32;
   INTERP1_POP_LANE1  : aliased HAL.UInt32;
   INTERP1_POP_FULL   : aliased HAL.UInt32;
   INTERP1_PEEK_LANE0 : aliased HAL.UInt32;
   INTERP1_PEEK_LANE1 : aliased HAL.UInt32;
   INTERP1_PEEK_FULL  : aliased HAL.UInt32;
   INTERP1_CTRL_LANE0 : aliased INTERP1_CTRL_LANE0_Register;
   INTERP1_CTRL_LANE1 : aliased INTERP1_CTRL_LANE1_Register;
   INTERP1_ACCUM0_ADD : aliased INTERP1_ACCUM0_ADD_Register;
   INTERP1_ACCUM1_ADD : aliased INTERP1_ACCUM1_ADD_Register;
   INTERP1_BASE_1AND0 : aliased HAL.UInt32;
   SPINLOCK0          : aliased HAL.UInt32;
   SPINLOCK1          : aliased HAL.UInt32;
   SPINLOCK2          : aliased HAL.UInt32;
   SPINLOCK3          : aliased HAL.UInt32;
   SPINLOCK4          : aliased HAL.UInt32;
   SPINLOCK5          : aliased HAL.UInt32;
   SPINLOCK6          : aliased HAL.UInt32;
   SPINLOCK7          : aliased HAL.UInt32;
   SPINLOCK8          : aliased HAL.UInt32;
   SPINLOCK9          : aliased HAL.UInt32;
   SPINLOCK10         : aliased HAL.UInt32;
   SPINLOCK11         : aliased HAL.UInt32;
   SPINLOCK12         : aliased HAL.UInt32;
   SPINLOCK13         : aliased HAL.UInt32;
   SPINLOCK14         : aliased HAL.UInt32;
   SPINLOCK15         : aliased HAL.UInt32;
   SPINLOCK16         : aliased HAL.UInt32;
   SPINLOCK17         : aliased HAL.UInt32;
   SPINLOCK18         : aliased HAL.UInt32;
   SPINLOCK19         : aliased HAL.UInt32;
   SPINLOCK20         : aliased HAL.UInt32;
   SPINLOCK21         : aliased HAL.UInt32;
   SPINLOCK22         : aliased HAL.UInt32;
   SPINLOCK23         : aliased HAL.UInt32;
   SPINLOCK24         : aliased HAL.UInt32;
   SPINLOCK25         : aliased HAL.UInt32;
   SPINLOCK26         : aliased HAL.UInt32;
   SPINLOCK27         : aliased HAL.UInt32;
   SPINLOCK28         : aliased HAL.UInt32;
   SPINLOCK29         : aliased HAL.UInt32;
   SPINLOCK30         : aliased HAL.UInt32;
   SPINLOCK31         : aliased HAL.UInt32;
end record
  with Volatile;

Record fields

CPUID

GPIO_IN

GPIO_HI_IN

GPIO_OUT

GPIO_OUT_SET

GPIO_OUT_CLR

GPIO_OUT_XOR

GPIO_OE

GPIO_OE_SET

GPIO_OE_CLR

GPIO_OE_XOR

GPIO_HI_OUT

GPIO_HI_OUT_SET

GPIO_HI_OUT_CLR

GPIO_HI_OUT_XOR

GPIO_HI_OE

GPIO_HI_OE_SET

GPIO_HI_OE_CLR

GPIO_HI_OE_XOR

FIFO_ST

FIFO_WR

FIFO_RD

SPINLOCK_ST

DIV_UDIVIDEND

DIV_UDIVISOR

DIV_SDIVIDEND

DIV_SDIVISOR

DIV_QUOTIENT

DIV_REMAINDER

DIV_CSR

INTERP0_ACCUM0

INTERP0_ACCUM1

INTERP0_BASE0

INTERP0_BASE1

INTERP0_BASE2

INTERP0_POP_LANE0

INTERP0_POP_LANE1

INTERP0_POP_FULL

INTERP0_PEEK_LANE0

INTERP0_PEEK_LANE1

INTERP0_PEEK_FULL

INTERP0_CTRL_LANE0

INTERP0_CTRL_LANE1

INTERP0_ACCUM0_ADD

INTERP0_ACCUM1_ADD

INTERP0_BASE_1AND0

INTERP1_ACCUM0

INTERP1_ACCUM1

INTERP1_BASE0

INTERP1_BASE1

INTERP1_BASE2

INTERP1_POP_LANE0

INTERP1_POP_LANE1

INTERP1_POP_FULL

INTERP1_PEEK_LANE0

INTERP1_PEEK_LANE1

INTERP1_PEEK_FULL

INTERP1_CTRL_LANE0

INTERP1_CTRL_LANE1

INTERP1_ACCUM0_ADD

INTERP1_ACCUM1_ADD

INTERP1_BASE_1AND0

SPINLOCK0

SPINLOCK1

SPINLOCK2

SPINLOCK3

SPINLOCK4

SPINLOCK5

SPINLOCK6

SPINLOCK7

SPINLOCK8

SPINLOCK9

SPINLOCK10

SPINLOCK11

SPINLOCK12

SPINLOCK13

SPINLOCK14

SPINLOCK15

SPINLOCK16

SPINLOCK17

SPINLOCK18

SPINLOCK19

SPINLOCK20

SPINLOCK21

SPINLOCK22

SPINLOCK23

SPINLOCK24

SPINLOCK25

SPINLOCK26

SPINLOCK27

SPINLOCK28

SPINLOCK29

SPINLOCK30

SPINLOCK31